| /external/mesa3d/src/intel/compiler/ |
| D | brw_fs_dead_code_eliminate.cpp | 95 for (unsigned i = 0; i < regs_written(inst); i++) in dead_code_eliminate()
114 for (unsigned i = 0; i < regs_written(inst); i++) { in dead_code_eliminate()
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| D | brw_schedule_instructions.cpp | 1164 for (unsigned r = 0; r < regs_written(inst); r++) { in calculate_deps()
1169 for (unsigned r = 0; r < regs_written(inst); r++) { in calculate_deps()
1191 for (unsigned r = 0; r < regs_written(inst); r++) in calculate_deps()
1292 for (unsigned r = 0; r < regs_written(inst); r++) in calculate_deps()
1295 for (unsigned r = 0; r < regs_written(inst); r++) { in calculate_deps()
1315 for (unsigned r = 0; r < regs_written(inst); r++) in calculate_deps()
1413 for (unsigned j = 0; j < regs_written(inst); ++j) { in calculate_deps()
1494 for (unsigned j = 0; j < regs_written(inst); ++j) in calculate_deps()
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| D | brw_fs_validate.cpp | 47 fsv_assert(inst->dst.offset / REG_SIZE + regs_written(inst) <= in validate()
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| D | brw_fs_cse.cpp | 206 unsigned written = regs_written(inst); in create_copy_instr()
242 assert(regs_written(copy) == written); in create_copy_instr()
291 int written = regs_written(entry->generator); in opt_cse_local()
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| D | brw_fs_register_coalesce.cpp | 233 channels_remaining -= regs_written(inst); in register_coalesce()
249 channels_remaining -= regs_written(inst); in register_coalesce()
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| D | brw_fs_live_variables.cpp | 134 for (unsigned j = 0; j < regs_written(inst); j++) { in setup_def_use()
358 !check_register_live_range(this, ip, inst->dst, regs_written(inst))) in validate()
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| D | brw_fs_reg_allocate.cpp | 1001 spill_costs[inst->dst.nr] += regs_written(inst) * block_scale; in set_spill_costs()
1214 fs_reg spill_src = alloc_spill_reg(regs_written(inst), ip); in spill_reg()
1260 regs_written(inst)); in spill_reg()
1263 subset_spill_offset, regs_written(inst)); in spill_reg()
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| D | brw_ir_performance.cpp | 1312 for (unsigned j = 0; j < regs_written(inst); j++) in issue_fs_inst()
1361 for (unsigned j = 0; j < regs_written(inst); j++) { in issue_fs_inst()
1429 for (unsigned j = 0; j < regs_written(inst); j++) in issue_vec4_instruction()
1466 for (unsigned j = 0; j < regs_written(inst); j++) { in issue_vec4_instruction()
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| D | brw_vec4_live_variables.cpp | 289 regs_written(inst))) in validate()
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| D | brw_vec4_cse.cpp | 210 regs_written(entry->generator)), in opt_cse_local()
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| D | brw_fs_scoreboard.cpp | 829 for (unsigned j = 0; j < regs_written(inst); j++) in update_inst_scoreboard()
934 for (unsigned j = 0; j < regs_written(inst); j++) { in gather_inst_dependencies()
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| D | brw_ir_vec4.h | 417 regs_written(const vec4_instruction *inst) in regs_written() function
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| D | brw_fs.cpp | 2034 for (unsigned j = 1; j < regs_written(inst); j++) in split_virtual_grfs()
2996 remap[dst] = alloc.allocate(regs_written(inst)); in opt_register_renaming()
3553 int write_len = regs_written(inst); in insert_gen4_pre_send_dependency_workarounds()
3586 for (unsigned i = 0; i < regs_written(scan_inst); i++) { in insert_gen4_pre_send_dependency_workarounds()
3624 int write_len = regs_written(inst); in insert_gen4_post_send_dependency_workarounds()
3938 low = fs_reg(VGRF, alloc.allocate(regs_written(inst)), in lower_mul_dword_inst()
3943 fs_reg high(VGRF, alloc.allocate(regs_written(inst)), inst->dst.type); in lower_mul_dword_inst()
4009 unsigned int q_regs = regs_written(inst); in lower_mul_qword_inst()
4561 payload.nr = bld.shader->alloc.allocate(regs_written(load)); in lower_fb_write_logical_send()
4589 inst->mlen = regs_written(load); in lower_fb_write_logical_send()
[all …]
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| D | brw_ir_fs.h | 441 regs_written(const fs_inst *inst) in regs_written() function
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| D | brw_fs_bank_conflicts.cpp | 516 p.require_contiguous(reg_of(inst->dst), regs_written(inst)); in shader_reg_partitioning()
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| D | brw_vec4.cpp | 1541 if (inst->dst.file == VGRF && regs_written(inst) > 1) in split_virtual_grfs()
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_atifs_to_tgsi.c | 53 bool regs_written[MAX_NUM_PASSES_ATI][MAX_NUM_FRAGMENT_REGISTERS_ATI]; member
129 if (t->regs_written[t->current_pass][src_type - GL_REG_0_ATI]) { in get_source()
323 if (t->regs_written[0][reg]) { in compile_setupinst()
341 t->regs_written[t->current_pass][r] = true; in compile_setupinst()
396 t->regs_written[t->current_pass][dstreg] = true; in compile_instruction()
406 if (t->regs_written[numPasses-1][0]) { in finalize_shader()
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| /external/mesa3d/docs/relnotes/ |
| D | 10.2.4.rst | 103 - i965/fs: Set correct number of regs_written for MCS fetches.
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| D | 17.0.5.rst | 73 - intel/fs: Use regs_written() in spilling cost heuristic for improved
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| D | 8.0.1.rst | 118 - i965/fs: Add a new fs_inst::regs_written function.
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| D | 11.2.2.rst | 99 - i965/fs: Properly report regs_written from SAMPLEINFO
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| D | 10.2.5.rst | 154 - i965/fs: Set correct number of regs_written for MCS fetches.
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| D | 9.1.3.rst | 117 - i965/fs: Avoid inappropriate optimization with regs_written > 1.
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| D | 9.1.4.rst | 154 - i965/fs: Bake regs_written into the IR instead of recomputing it
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