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Searched refs:rs1 (Results 1 – 25 of 53) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
D	RISCVInstrInfoD.td	35 (ins FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, frmarg:$funct3), 36 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">; 39 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3", 40 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 45 (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">, 51 (ins FPR64:$rs1, FPR64:$rs2, frmarg:$funct3), opcodestr, 52 "$rd, $rs1, $rs2, $funct3">, 56 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2", 57 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>; 62 (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">, [all …]
D	RISCVInstrInfoC.td	220 : RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SP:$rs1, opnd:$imm), 221 OpcodeStr, "$rd, ${imm}(${rs1})">; 226 : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SP:$rs1, opnd:$imm), 227 OpcodeStr, "$rs2, ${imm}(${rs1})">; 232 : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPRC:$rs1, opnd:$imm), 233 OpcodeStr, "$rd, ${imm}(${rs1})">; 238 : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2, GPRC:$rs1, opnd:$imm), 239 OpcodeStr, "$rs2, ${imm}(${rs1})">; 244 : RVInst16CB<funct3, 0b01, (outs), (ins cls:$rs1, simm9_lsb0:$imm), 245 OpcodeStr, "$rs1, $imm"> { [all …]
D	RISCVInstrInfoF.td	53 (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3), 54 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">; 57 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3", 58 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 63 (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">, 69 (ins FPR32:$rs1, FPR32:$rs2, frmarg:$funct3), opcodestr, 70 "$rd, $rs1, $rs2, $funct3">; 73 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2", 74 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>; 79 : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1), [all …]
D	RISCVInstrInfo.td	`300 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12), 301 opcodestr, "$rs1, $rs2, $imm12">, 309 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), 310 opcodestr, "$rd, ${imm12}(${rs1})">; 318 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12), 319 opcodestr, "$rs2, ${imm12}(${rs1})">; 323 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), 324 opcodestr, "$rd, $rs1, $imm12">, 330 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr, 331 "$rd, $rs1, $shamt">, [all …]`
D	RISCVInstrInfoM.td	`74 def : Pat<(sext_inreg (mul GPR:$rs1, GPR:$rs2), i32), 75 (MULW GPR:$rs1, GPR:$rs2)>; 84 def : Pat<(zexti32 (riscv_divuw (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))), 85 (DIVU GPR:$rs1, GPR:$rs2)>; 86 def : Pat<(zexti32 (riscv_remuw (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))), 87 (REMU GPR:$rs1, GPR:$rs2)>; 92 def : Pat<(srem (sexti32 GPR:$rs1), (sexti32 GPR:$rs2)), 93 (REMW GPR:$rs1, GPR:$rs2)>; 94 def : Pat<(sext_inreg (srem (sexti32 GPR:$rs1), 96 (REMW GPR:$rs1, GPR:$rs2)>;`
D	RISCVInstrFormatsC.td	`39 bits<5> rs1; 43 let Inst{11-7} = rs1; 56 bits<5> rs1; 72 bits<5> rs1; 97 bits<3> rs1; 100 let Inst{9-7} = rs1; 112 bits<3> rs1; 115 let Inst{9-7} = rs1; 124 bits<3> rs1; 127 let Inst{9-7} = rs1; [all …]`
D	RISCVInstrFormats.td	`149 bits<5> rs1; 154 let Inst{19-15} = rs1; 165 bits<5> rs1; 172 let Inst{19-15} = rs1; 183 bits<5> rs1; 190 let Inst{19-15} = rs1; 200 bits<5> rs1; 206 let Inst{19-15} = rs1; 216 bits<5> rs1; 220 let Inst{19-15} = rs1; [all …]`
D	RISCVInstrInfoA.td	39 (outs GPR:$rd), (ins GPRMemAtomic:$rs1), 40 opcodestr, "$rd, $rs1"> { 54 (outs GPR:$rd), (ins GPRMemAtomic:$rs1, GPR:$rs2), 55 opcodestr, "$rd, $rs2, $rs1">; 65 def : Pat<(StoreOp GPR:$rs1, StTy:$rs2), (Inst StTy:$rs2, GPR:$rs1, 0)>; 66 def : Pat<(StoreOp AddrFI:$rs1, StTy:$rs2), (Inst StTy:$rs2, AddrFI:$rs1, 0)>; 67 def : Pat<(StoreOp (add GPR:$rs1, simm12:$imm12), StTy:$rs2), 68 (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>; 69 def : Pat<(StoreOp (add AddrFI:$rs1, simm12:$imm12), StTy:$rs2), 70 (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>; [all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/RISCV/
D	RISCVGenDAGISel.inc	66 /* 32/ OPC_RecordChild0, // #0 = $rs1 79 …and:{ :[i32] } (riscv_divuw:{ :[i32] } (and:{ :[i32] } GPR:{ :[i32] }:$rs1, 4294967295:{ :[i3… 80 // Dst: (DIVU:{ :[i32] } GPR:{ :[i32] }:$rs1, GPR:{ :[i32] }:$rs2) 85 …and:{ :[i32] } (riscv_divuw:{ :[i32] } (and:{ :[i32] } GPR:{ :[i32] }:$rs1, 4294967295:{ :[i3… 86 // Dst: (DIVU:{ :[i32] } GPR:{ :[i32] }:$rs1, GPR:{ :[i32] }:$rs2) 92 …and:{ :[i64] } (riscv_divuw:{ :[i64] } (and:{ :[i64] } GPR:{ :[i64] }:$rs1, 4294967295:{ :[i6… 93 // Dst: (DIVU:{ :[i64] } GPR:{ :[i64] }:$rs1, GPR:{ :[i64] }:$rs2) 106 …and:{ :[i32] } (riscv_divuw:{ :[i32] } (and:{ :[i32] } GPR:{ :[i32] }:$rs1, 4294967295:{ :[i3… 107 // Dst: (DIVU:{ :[i32] } GPR:{ :[i32] }:$rs1, GPR:{ :[i32] }:$rs2) 112 …and:{ :[i32] } (riscv_divuw:{ :[i32] } (and:{ :[i32] } GPR:{ :[i32] }:$rs1, 4294967295:{ :[i3… [all …]
D	RISCVGenGlobalISel.inc	360 … :[i32] } GPR:{ :[i32] }:$rs1, (imm:{ :[i32] })<<P:Predicate_simm12>>:$imm12) => (ADDI:{ :[i… 363 GIR_Copy, /NewInsnID/0, /OldInsnID/0, /OpIdx/1, // rs1 377 … :[i32] } GPR:{ :[i32] }:$rs1, (imm:{ :[i32] })<<P:Predicate_simm12>>:$imm12) => (ADDI:{ :[i… 380 GIR_Copy, /NewInsnID/0, /OldInsnID/0, /OpIdx/1, // rs1 389 …// (add:{ :[i32] } GPR:{ :[i32] }:$rs1, GPR:{ :[i32] }:$rs2) => (ADD:{ :[i32] } GPR:{ :[i32… 397 …// (add:{ :[i32] } GPR:{ :[i32] }:$rs1, GPR:{ :[i32] }:$rs2) => (ADD:{ :[i32] } GPR:{ :[i32… 419 … :[i64] } GPR:{ :[i64] }:$rs1, (imm:{ :[i64] })<<P:Predicate_simm12>>:$imm12) => (ADDI:{ :[i… 422 GIR_Copy, /NewInsnID/0, /OldInsnID/0, /OpIdx/1, // rs1 431 …// (add:{ :[i64] } GPR:{ :[i64] }:$rs1, GPR:{ :[i64] }:$rs2) => (ADD:{ :[i64] } GPR:{ :[i64… 454 …// (sub:{ :[i32] } GPR:{ :[i32] }:$rs1, GPR:{ :[i32] }:$rs2) => (SUB:{ :[i32] } GPR:{ :[i32… [all …]
D	RISCVGenCompressInstEmitter.inc	`147 // c.mv $rs1, $rs2 149 // Operand: rs1 160 // c.mv $rs1, $rs2 162 // Operand: rs1 173 // c.add $rs1, $rs2 177 // Operand: rs1 188 // c.add $rs1, $rs2 192 // Operand: rs1 206 // c.addi4spn $rd, $rs1, $imm 210 // Operand: rs1 [all …]`
D	RISCVGenMCPseudoLowering.inc	`32 // Operand: rs1 47 // Operand: rs1 61 // Operand: rs1 74 // Operand: rs1`
/external/llvm/lib/Target/Sparc/
D	SparcInstrVIS.td	`21 (outs RC:$rd), (ins RC:$rs1, RC:$rs2), 22 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 27 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 28 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 31 let rd = 0, rs1 = 0, rs2 = 0 in 35 // For VIS Instructions with only rs1, rd operands. 39 (outs RC:$rd), (ins RC:$rs1), 40 !strconcat(OpcStr, " $rs1, $rd"), []>; 43 let rs1 = 0 in 50 let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in [all …]`
D	SparcInstrInfo.td	292 (outs RC:$rd), (ins RC:$rs1, RC:$rs2), 293 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 294 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))], 297 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13), 298 !strconcat(OpcStr, " $rs1, $simm13, $rd"), 299 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))], 307 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 308 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [], 311 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 312 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [], [all …]
D	SparcInstrAliases.td	143 // t<cond> %icc, rs1 + rs2 144 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"), 145 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>, 153 // t<cond> %xcc, rs1 + rs2 154 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"), 155 (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>, 164 // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2 165 //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"), 166 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>, 173 // t<cond> %icc, rs1 + imm [all …]
D	SparcInstr64Bit.td	`167 (ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym), 168 "add $rs1, $rs2, $rd, $sym", 170 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>; 193 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 194 "mulx $rs1, $rs2, $rd", 195 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>; 197 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 198 "mulx $rs1, $simm13, $rd", 199 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>; 204 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), [all …]`
D	SparcInstrFormats.td	`91 bits<5> rs1; 101 let Inst{18-14} = rs1; 115 bits<5> rs1; 119 let Inst{18-14} = rs1; 177 let rs1 = 0; 230 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), 231 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 232 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))], 234 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt), 235 !strconcat(OpcStr, " $rs1, $shcnt, $rd"), [all …]`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
D	SparcInstrVIS.td	`20 (outs RC:$rd), (ins RC:$rs1, RC:$rs2), 21 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 26 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 27 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 30 let rd = 0, rs1 = 0, rs2 = 0 in 34 // For VIS Instructions with only rs1, rd operands. 38 (outs RC:$rd), (ins RC:$rs1), 39 !strconcat(OpcStr, " $rs1, $rd"), []>; 42 let rs1 = 0 in 49 let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in [all …]`
D	SparcInstrInfo.td	312 (outs RC:$rd), (ins RC:$rs1, RC:$rs2), 313 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 314 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))], 317 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13), 318 !strconcat(OpcStr, " $rs1, $simm13, $rd"), 319 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))], 327 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 328 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [], 331 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 332 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [], [all …]
D	SparcInstrAliases.td	142 // t<cond> %icc, rs1 + rs2 143 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"), 144 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>, 152 // t<cond> %xcc, rs1 + rs2 153 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"), 154 (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>, 163 // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2 164 //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"), 165 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>, 172 // t<cond> %icc, rs1 + imm [all …]
D	SparcInstr64Bit.td	`166 (ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym), 167 "add $rs1, $rs2, $rd, $sym", 169 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>; 192 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 193 "mulx $rs1, $rs2, $rd", 194 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>; 196 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 197 "mulx $rs1, $simm13, $rd", 198 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>; 203 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), [all …]`
D	SparcInstrFormats.td	`90 bits<5> rs1; 100 let Inst{18-14} = rs1; 114 bits<5> rs1; 118 let Inst{18-14} = rs1; 176 let rs1 = 0; 229 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), 230 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 231 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))], 233 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt), 234 !strconcat(OpcStr, " $rs1, $shcnt, $rd"), [all …]`
/external/elfutils/libcpu/
D	riscv_disasm.c	`181 uint16_t rs1; in riscv_disasm() local 201 rs1 = (first >> 7) & 0x1f; in riscv_disasm() 204 if (rs1 == 0) in riscv_disasm() 209 op[0] = op[1] = REG (rs1); in riscv_disasm() 215 rs1 = (first >> 7) & 0x1f; in riscv_disasm() 216 op[0] = op[1] = REG (rs1); in riscv_disasm() 220 mne = rs1 == 0 ? "c.slli" : "slli"; in riscv_disasm() 405 rs1 = (first >> 7) & 0x1f; in riscv_disasm() 407 op[0] = REG (rs1); in riscv_disasm() 413 if (rs1 == 1) in riscv_disasm() [all …]`
/external/eigen/test/
D	schur_real.cpp	`59 RealSchur<MatrixType> rs1; in schur() local 60 rs1.compute(A); in schur() 62 VERIFY_IS_EQUAL(rs1.info(), Success); in schur() 64 VERIFY_IS_EQUAL(rs1.matrixT(), rs2.matrixT()); in schur() 65 VERIFY_IS_EQUAL(rs1.matrixU(), rs2.matrixU()); in schur() 71 VERIFY_IS_EQUAL(rs3.matrixT(), rs1.matrixT()); in schur() 72 VERIFY_IS_EQUAL(rs3.matrixU(), rs1.matrixU()); in schur() 89 VERIFY_IS_EQUAL(rs1.matrixT(), rsOnlyT.matrixT()); in schur()`
/external/javasqlite/src/main/java/SQLite/JDBC2z/
D	JDBCDatabaseMetaData.java	732 JDBCResultSet rs1 = null; in getBestRowIdentifier() local 742 rs1 = (JDBCResultSet) in getBestRowIdentifier() 766 rs1 != null && rs1.tr != null && rs1.tr.nrows > 0) { in getBestRowIdentifier() 772 for (int i = 0; i < rs1.tr.ncolumns; i++) { in getBestRowIdentifier() 773 h1.put(rs1.tr.column[i], Integer.valueOf(i)); // android-changed in getBestRowIdentifier() 806 for (int m = 0; m < rs1.tr.nrows; m++) { in getBestRowIdentifier() 807 String r1[] = (String [])(rs1.tr.rows.elementAt(m)); in getBestRowIdentifier() 904 JDBCResultSet rs1 = null; in getPrimaryKeys() local 906 rs1 = (JDBCResultSet) in getPrimaryKeys() 913 if (rs1 == null \|\| rs1.tr == null \|\| rs1.tr.nrows <= 0) { in getPrimaryKeys() [all …]

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