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/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.rsq.ll4 declare float @llvm.amdgcn.rsq.f32(float) #0
5 declare double @llvm.amdgcn.rsq.f64(double) #0
10 %rsq = call float @llvm.amdgcn.rsq.f32(float %src) #0
11 store float %rsq, float addrspace(1)* %out, align 4
19 %rsq = call float @llvm.amdgcn.rsq.f32(float 4.0) #0
20 store float %rsq, float addrspace(1)* %out, align 4
27 %rsq = call float @llvm.amdgcn.rsq.f32(float 100.0) #0
28 store float %rsq, float addrspace(1)* %out, align 4
35 %rsq = call double @llvm.amdgcn.rsq.f64(double %src) #0
36 store double %rsq, double addrspace(1)* %out, align 4
[all …]
Dllvm.amdgcn.rsq.legacy.ll3 declare float @llvm.amdgcn.rsq.legacy(float) #0
8 %rsq = call float @llvm.amdgcn.rsq.legacy(float %src) #0
9 store float %rsq, float addrspace(1)* %out, align 4
17 %rsq = call float @llvm.amdgcn.rsq.legacy(float 4.0) #0
18 store float %rsq, float addrspace(1)* %out, align 4
25 %rsq = call float @llvm.amdgcn.rsq.legacy(float 100.0) #0
26 store float %rsq, float addrspace(1)* %out, align 4
33 %rsq = call float @llvm.amdgcn.rsq.legacy(float undef)
34 store float %rsq, float addrspace(1)* %out, align 4
Dllvm.AMDGPU.rsq.ll5 declare float @llvm.AMDGPU.rsq.f32(float) nounwind readnone
11 %rsq = call float @llvm.AMDGPU.rsq.f32(float %src) nounwind readnone
12 store float %rsq, float addrspace(1)* %out, align 4
21 %rsq = call float @llvm.AMDGPU.rsq.f32(float 4.0) nounwind readnone
22 store float %rsq, float addrspace(1)* %out, align 4
30 %rsq = call float @llvm.AMDGPU.rsq.f32(float 100.0) nounwind readnone
31 store float %rsq, float addrspace(1)* %out, align 4
Dvi-removed-intrinsics.ll5 declare float @llvm.amdgcn.rsq.legacy(float) #0
8 %rsq = call float @llvm.amdgcn.rsq.legacy(float %src), !dbg !4
9 store float %rsq, float addrspace(1)* %out, align 4
Dllvm.amdgcn.rsq.clamp.ll4 declare float @llvm.amdgcn.rsq.clamp.f32(float) #1
5 declare double @llvm.amdgcn.rsq.clamp.f64(double) #1
18 %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float %src)
35 %rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src)
43 %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float undef)
Dllvm.AMDGPU.rsq.clamped.ll5 ; FIXME: Uses of this should be moved to llvm.amdgcn.rsq.clamped, and
8 declare float @llvm.AMDGPU.rsq.clamped.f32(float) nounwind readnone
22 %rsq_clamped = call float @llvm.AMDGPU.rsq.clamped.f32(float %src) nounwind readnone
Dllvm.AMDGPU.rsq.clamped.f64.ll4 declare double @llvm.AMDGPU.rsq.clamped.f64(double) nounwind readnone
18 %rsq_clamped = call double @llvm.AMDGPU.rsq.clamped.f64(double %src) nounwind readnone
Dpv.ll106 %98 = call float @llvm.AMDGPU.rsq.clamped.f32(float %97)
228 declare float @llvm.AMDGPU.rsq.clamped.f32(float) #1
Dload-input-fold.ll104 declare float @llvm.AMDGPU.rsq(float) #1
/external/fec/
Dsim.c10 double fac,rsq,v1,v2; in normal_rand() local
25 rsq = v1*v1 + v2*v2; in normal_rand()
26 } while(rsq >= 1.0 || rsq == 0.0); in normal_rand()
27 fac = sqrt(-2.0*log(rsq)/rsq); in normal_rand()
/external/mesa3d/src/intel/tools/tests/gen7/
Dmath.asm25 math rsq(8) g69<1>.xF (abs)g68<4>.xF null<4>F { align16 1Q };
26 math rsq(8) g47<1>F g46<8,8,1>F null<8,8,1>F { align1 1Q };
27 math rsq(16) g84<1>F g82<8,8,1>F null<8,8,1>F { align1 1H };
34 math.sat rsq(8) g116<1>F (abs)g6<4>.xF null<4>F { align16 1Q };
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dmath.asm29 math rsq(8) g69<1>.xF (abs)g68<4>.xF null<4>F { align16 1Q };
32 math rsq(8) g127<1>F g2.1<0,1,0>F null<8,8,1>F { align1 1Q };
33 math rsq(16) g126<1>F g2.1<0,1,0>F null<8,8,1>F { align1 1H };
42 math.sat rsq(8) g116<1>F (abs)g6<4>.xF null<4>F { align16 1Q };
/external/mesa3d/src/gallium/drivers/radeonsi/glsl_tests/
Dsqrt.glsl31 ; FUNC-LABEL: {{^}}@rsq:
37 #shader fs rsq
/external/mesa3d/src/intel/tools/tests/gen8/
Dmath.asm7 math rsq(8) g5<1>F g2<8,8,1>F null<8,8,1>F { align1 1Q };
18 math rsq(16) g68<1>F g66<8,8,1>F null<8,8,1>F { align1 1H };
29 math.sat rsq(8) g127<1>F (abs)g7<8,8,1>F null<8,8,1>F { align1 1Q };
/external/mesa3d/src/intel/tools/tests/gen9/
Dmath.asm7 math rsq(8) g5<1>F g2<8,8,1>F null<8,8,1>F { align1 1Q };
18 math rsq(16) g68<1>F g66<8,8,1>F null<8,8,1>F { align1 1H };
29 math.sat rsq(8) g127<1>F (abs)g7<8,8,1>F null<8,8,1>F { align1 1Q };
/external/clang/test/CodeGenOpenCL/
Dbuiltins-amdgcn.cl91 // CHECK: call float @llvm.amdgcn.rsq.f32
98 // CHECK: call double @llvm.amdgcn.rsq.f64
105 // CHECK: call float @llvm.amdgcn.rsq.clamp.f32
112 // CHECK: call double @llvm.amdgcn.rsq.clamp.f64
267 // CHECK: call float @llvm.amdgcn.rsq.f32
274 // CHECK: call double @llvm.amdgcn.rsq.f64
Dbuiltins-r600.cl5 // CHECK: call float @llvm.r600.rsq.f32
13 // XCHECK: call double @llvm.r600.rsq.f64
/external/mesa3d/src/intel/tools/tests/gen6/
Dmath.asm14 math rsq(8) g71<1>F g70<4,4,1>F null<8,8,1>F { align1 1Q };
16 math rsq(8) g3<1>F g5<8,8,1>F null<8,8,1>F { align1 2Q };
/external/llvm/lib/Target/AMDGPU/
DAMDGPUIntrinsics.td32 // Deprecated in favor of llvm.amdgcn.rsq
/external/mesa3d/docs/relnotes/
D10.2.3.rst68 - radeon/llvm: Use the llvm.rsq.clamped intrinsic for RSQ
D20.0.3.rst165 - ac/nir: use llvm.amdgcn.rsq for nir_op_frsq
/external/mesa3d/src/freedreno/ir3/tests/
Ddelay.c47 rsq r0.x, r0.x
/external/mesa3d/src/intel/tools/tests/gen4/
Dsend.asm74 math MsgDesc: rsq mlen 1 rlen 1 { align16 };
82 math MsgDesc: rsq scalar mlen 1 rlen 1 { align1 };
/external/mesa3d/src/intel/tools/tests/gen4.5/
Dsend.asm88 math MsgDesc: rsq mlen 1 rlen 1 { align16 };
96 math MsgDesc: rsq scalar mlen 1 rlen 1 { align1 compr };
/external/mesa3d/src/compiler/glsl/
Dir_builder.h155 ir_expression *rsq(operand a);

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