1 /* 2 * Copyright 2021 NXP 3 * SPDX-License-Identifier: BSD-3-Clause 4 * 5 */ 6 7 #ifndef _INPUT_H_ 8 #define _INPUT_H_ 9 10 enum dram_types { 11 DDR4, 12 DDR3, 13 LPDDR4, 14 LPDDR3, 15 LPDDR2, 16 DDR5, 17 }; 18 19 enum dimm_types { 20 UDIMM, 21 SODIMM, 22 RDIMM, 23 LRDIMM, 24 NODIMM, 25 }; 26 27 struct input_basic { 28 enum dram_types dram_type; 29 enum dimm_types dimm_type; 30 int lp4x_mode; /* 0x1 = lpddr4x mode, when dram_type is lpddr4 31 */ 32 /* not used for protocols other than lpddr4 */ 33 int num_dbyte; /* number of dbytes physically instantiated */ 34 int num_active_dbyte_dfi0; /* number of active dbytes to be 35 * controlled by dfi0 36 */ 37 int num_active_dbyte_dfi1; /* number of active dbytes to be 38 * controlled by dfi1. Not used for 39 * protocols other than lpddr3 and 40 * lpddr4 41 */ 42 int num_anib; /* number of anibs physically instantiated */ 43 int num_rank_dfi0; /* number of ranks in dfi0 channel */ 44 int num_rank_dfi1; /* number of ranks in dfi1 channel */ 45 int dram_data_width; /* 4,8,16 or 32 depending on protocol and dram 46 * type 47 */ 48 int num_pstates; 49 int frequency; /* memclk frequency in mhz -- round up */ 50 int pll_bypass; /* pll bypass enable */ 51 int dfi_freq_ratio; /* selected dfi frequency ratio */ 52 int dfi1exists; /* whether they phy config has dfi1 channel */ 53 int train2d; 54 int hard_macro_ver; 55 int read_dbienable; 56 int dfi_mode; /* no longer used */ 57 }; 58 59 struct input_advanced { 60 int d4rx_preamble_length; 61 int d4tx_preamble_length; 62 int ext_cal_res_val; /* external pull-down resistor */ 63 int is2ttiming; 64 int odtimpedance; 65 int tx_impedance; 66 int atx_impedance; 67 int mem_alert_en; 68 int mem_alert_puimp; 69 int mem_alert_vref_level; 70 int mem_alert_sync_bypass; 71 int dis_dyn_adr_tri; 72 int phy_mstr_train_interval; 73 int phy_mstr_max_req_to_ack; 74 int wdqsext; 75 int cal_interval; 76 int cal_once; 77 int dram_byte_swap; 78 int rx_en_back_off; 79 int train_sequence_ctrl; 80 int phy_gen2_umctl_opt; 81 int phy_gen2_umctl_f0rc5x; 82 int tx_slew_rise_dq; 83 int tx_slew_fall_dq; 84 int tx_slew_rise_ac; 85 int tx_slew_fall_ac; 86 int enable_high_clk_skew_fix; 87 int disable_unused_addr_lns; 88 int phy_init_sequence_num; 89 int cs_mode; /* rdimm */ 90 int cast_cs_to_cid; /* rdimm */ 91 }; 92 93 struct input { 94 struct input_basic basic; 95 struct input_advanced adv; 96 unsigned int mr[7]; 97 unsigned int cs_d0; 98 unsigned int cs_d1; 99 unsigned int mirror; 100 unsigned int odt[4]; 101 unsigned int rcw[16]; 102 unsigned int rcw3x; 103 unsigned int vref; 104 }; 105 106 #endif 107