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Searched refs:s_and_saveexec_b64 (Results 1 – 20 of 20) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dcgp-addressing-modes.ll42 ; GCN: s_and_saveexec_b64
69 ; GCN: s_and_saveexec_b64
96 ; GCN: s_and_saveexec_b64
128 ; GCN: s_and_saveexec_b64
165 ; GCN: s_and_saveexec_b64
197 ; GCN: s_and_saveexec_b64
233 ; GCN: s_and_saveexec_b64
262 ; GCN: s_and_saveexec_b64
293 ; GCN: s_and_saveexec_b64
325 ; GCN: s_and_saveexec_b64
[all …]
Di1-copy-phi.ll6 ; SI: s_and_saveexec_b64
10 ; SI: s_and_saveexec_b64
Dsi-lower-control-flow-unreachable-block.ll5 ; GCN: s_and_saveexec_b64
30 ; GCN: s_and_saveexec_b64
Duniform-loop-inside-nonuniform.ll7 ; CHECK: s_and_saveexec_b64
34 ;CHECK: s_and_saveexec_b64
Dvalu-i1.ll47 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
73 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
116 ; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc
132 ; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]]
Dsi-annotate-cfg-loop-assert.ll4 ; CHECK s_and_saveexec_b64
Dsubreg-coalescer-undef-use.ll12 ; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc
Dllvm.amdgcn.ps.live.ll36 ; CHECK_DAG: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[HELPER]]
Duniform-cfg.ll309 ; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
339 ; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
366 ; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
Dindirect-addressing-si.ll216 ; CHECK: s_and_saveexec_b64 vcc, vcc
229 ; CHECK: s_and_saveexec_b64 vcc, vcc
272 ; CHECK: s_and_saveexec_b64 vcc, vcc
286 ; CHECK: s_and_saveexec_b64 vcc, vcc
Dret_jump.ll10 ; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc
Dwqm.ll87 ;CHECK: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[ORIG]]
256 ;CHECK: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[ORIG]]
289 ;CHECK: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[ORIG]]
Dinline-asm.ll27 ; CHECK: s_and_saveexec_b64
Dskip-if-dead.ll203 ; CHECK-NEXT: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], vcc
Dllvm.amdgcn.div.fmas.ll139 ; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc
/external/llvm/test/Object/AMDGPU/
Dobjdump.s17 s_and_saveexec_b64 s[0:1], vcc
30 s_and_saveexec_b64 s[0:1], vcc
/external/llvm/test/MC/AMDGPU/
Dsop1.s179 s_and_saveexec_b64 s[2:3], s[4:5] label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt126 # VI: s_and_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x20,0x82,0xbe]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td253 def S_AND_SAVEEXEC_B64 : SOP1_64 <"s_and_saveexec_b64">;
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td163 defm S_AND_SAVEEXEC_B64 : SOP1_64 <sop1<0x24, 0x20>, "s_and_saveexec_b64", []>;