Home
last modified time | relevance | path

Searched refs:s_ashr_i32 (Results 1 – 11 of 11) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dload-constant-i32.ll93 ; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[SLO]], 31
120 ; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[LO]], 31
142 ; GCN-DAG: s_ashr_i32
143 ; GCN-DAG: s_ashr_i32
168 ; GCN: s_ashr_i32
169 ; GCN: s_ashr_i32
170 ; GCN: s_ashr_i32
171 ; GCN: s_ashr_i32
204 ; GCN: s_ashr_i32
205 ; GCN: s_ashr_i32
[all …]
Dsign_extend.ll15 ; GCN: s_ashr_i32
39 ; GCN: s_ashr_i32
70 ; GCN-DAG: s_ashr_i32 [[EXT3:s[0-9]+]], [[VAL]], 24
126 ; GCN-DAG: s_ashr_i32 s{{[0-9]+}}, s{{[0-9]+}}, 16
Dload-constant-i16.ll140 ; GCN-DAG: s_ashr_i32
194 ; GCN-DAG: s_ashr_i32
229 ; GCN-DAG: s_ashr_i32
251 ; GCN-DAG: s_ashr_i32
274 ; GCN-DAG: s_ashr_i32
Dsra.ll205 ; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31
232 ; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31
Dload-constant-i8.ll197 ; GCN-DAG: s_ashr_i32
231 ; GCN-DAG: s_ashr_i32
Dsext-in-reg.ll138 ; XSI: s_ashr_i32 {{v[0-9]+}}, [[EXTRACT]], 31
/external/llvm/test/MC/AMDGPU/
Dsop2.s123 s_ashr_i32 s2, s4, s6 label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_vi.txt63 # VI: s_ashr_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x90]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td538 def S_ASHR_I32 : SOP2_32 <"s_ashr_i32",
/external/mesa3d/src/amd/compiler/
Daco_instruction_selection.cpp603 … Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), tmp, Operand(31u)); in convert_int()
1470 emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true); in visit_alu_instr()
2418 … Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u)); in visit_alu_instr()
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td290 defm S_ASHR_I32 : SOP2_32 <sop2<0x22, 0x20>, "s_ashr_i32",