Searched refs:s_bcnt1_i32_b64 (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | ctpop64.ll | 16 ; GCN: s_bcnt1_i32_b64 [[SRESULT:s[0-9]+]], [[SVAL]]
61 ; GCN: s_bcnt1_i32_b64
62 ; GCN: s_bcnt1_i32_b64
72 ; GCN: s_bcnt1_i32_b64
73 ; GCN: s_bcnt1_i32_b64
74 ; GCN: s_bcnt1_i32_b64
75 ; GCN: s_bcnt1_i32_b64
119 ; GCN-DAG: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}}
146 ; GCN: s_bcnt1_i32_b64 [[SRESULT0:s[0-9]+]],
147 ; GCN: s_bcnt1_i32_b64 [[SRESULT1:s[0-9]+]],
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| /external/llvm/test/MC/AMDGPU/ |
| D | sop1.s | 103 s_bcnt1_i32_b64 s1, s[2:3] label
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| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | sop1_vi.txt | 69 # VI: s_bcnt1_i32_b64 s1, s[2:3] ; encoding: [0x02,0x0d,0x81,0xbe]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SOPInstructions.td | 195 def S_BCNT1_I32_B64 : SOP1_32_64 <"s_bcnt1_i32_b64",
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 126 defm S_BCNT1_I32_B64 : SOP1_32_64 <sop1<0x10, 0x0d>, "s_bcnt1_i32_b64", []>;
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| /external/mesa3d/docs/relnotes/ |
| D | 20.0.0.rst | 3402 - aco: Fix operand of s_bcnt1_i32_b64 in emit_boolean_reduce.
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_instruction_selection.cpp | 2870 bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src); in visit_alu_instr()
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