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Searched refs:s_getpc_b64 (Results 1 – 8 of 8) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dglobal-variable-relocs.ll16 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
30 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
44 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
61 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
78 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
95 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
112 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
129 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
146 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
163 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
[all …]
Dglobal-constant.ll8 ; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
11 ; GCN: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
/external/llvm/test/MC/AMDGPU/
Dsop1.s163 s_getpc_b64 s[2:3] label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt114 # VI: s_getpc_b64 s[2:3] ; encoding: [0x00,0x1c,0x82,0xbe]
/external/mesa3d/src/amd/compiler/
Daco_assembler.cpp54 uint32_t opcode = ctx.opcode[(int)aco_opcode::s_getpc_b64]; in emit_instruction()
853 instr.reset(bld.sop1(aco_opcode::s_getpc_b64, branch->definitions[0]).instr); in emit_long_jump()
Daco_insert_NOPs.cpp585 instr->opcode == aco_opcode::s_getpc_b64 || in instr_is_branch()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td228 def S_GETPC_B64 : SOP1_64_0 <"s_getpc_b64",
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td156 defm S_GETPC_B64 : SOP1_64_0 <sop1<0x1f, 0x1c>, "s_getpc_b64", []>;