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Searched refs:s_or_b64 (Results 1 – 25 of 25) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dendcf-loop-header.ll4 ; loop block. This intrinsic will be lowered to s_or_b64 by the code
10 ; CHECK: s_or_b64 exec, exec
13 ; CHECK-NOT: s_or_b64 exec, exec
Dvalu-i1.ll55 ; SI: s_or_b64 exec, exec, [[BR_SREG]]
139 ; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]]
142 ; SI: s_or_b64 exec, exec, [[ORNEG2]]
143 ; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[TMP]]
148 ; SI: s_or_b64 exec, exec, [[COND_STATE]]
Dsi-lower-control-flow-unreachable-block.ll9 ; GCN: s_or_b64 exec, exec
34 ; GCN: s_or_b64 exec, exec
Dcgp-addressing-modes.ll45 ; GCN: s_or_b64 exec
72 ; GCN: s_or_b64 exec
99 ; GCN: s_or_b64 exec
235 ; GCN: s_or_b64 exec, exec
264 ; GCN: s_or_b64 exec, exec
297 ; GCN: s_or_b64 exec, exec
329 ; GCN: s_or_b64 exec, exec
360 ; GCN: s_or_b64 exec, exec
390 ; GCN: s_or_b64 exec, exec
428 ; GCN: s_or_b64 exec, exec
Dsi-annotate-cf.ll8 ; SI: s_or_b64
30 ; FIXME: This could be folded into the s_or_b64 instruction
36 ; SI: s_or_b64 [[BREAK:s\[[0-9]+:[0-9]+\]]], vcc, [[ZERO]]
Dsi-annotate-cfg-loop-assert.ll6 ; CHECK s_or_b64 exec, exec
Dor.ll87 ; SI: s_or_b64
158 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
171 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
Drotl.i64.ll8 ; BOTH: s_or_b64
Dsubreg-coalescer-undef-use.ll18 ; CHECK: s_or_b64 exec, exec, s[2:3]
Drotr.i64.ll8 ; BOTH: s_or_b64
Dret_jump.ll18 ; GCN-NEXT: s_or_b64 exec, exec, [[XOR_EXEC]]
Dskip-if-dead.ll221 ; CHECK: s_or_b64 exec, exec, [[SAVEEXEC]]
Dllvm.amdgcn.div.fmas.ll148 ; SI: s_or_b64 exec, exec, [[SAVE]]
Dmadmk.ll190 ; SI: s_or_b64
Duniform-cfg.ll370 ; SI: s_or_b64 exec, exec, [[MASK]]
Dwqm.ll129 ;CHECK: s_or_b64 exec, exec,
Dllvm.amdgcn.class.ll457 ; SI: s_or_b64
Dsi-spill-cf.ll7 ; SI: s_or_b64 exec, exec, [[SAVED:s\[[0-9]+:[0-9]+\]|[a-z]+]]
/external/mesa3d/src/amd/compiler/tests/
Dtest_optimizer.cpp175 writeout(0, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
181 writeout(1, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
187 writeout(2, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
218 writeout(6, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
226 writeout(7, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
/external/llvm/test/MC/AMDGPU/
Dsop2.s55 s_or_b64 s[2:3], s[4:5], s[6:7] label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_vi.txt12 # VI: s_or_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x87]
/external/mesa3d/src/amd/compiler/
Daco_optimizer.cpp1443 case aco_opcode::s_or_b64: in label_instruction()
1626 bool is_or = instr->opcode == aco_opcode::s_or_b64 || instr->opcode == aco_opcode::s_or_b32; in combine_ordering_test()
1726 bool is_or = instr->opcode == aco_opcode::s_or_b64 || instr->opcode == aco_opcode::s_or_b32; in combine_comparison_ordering()
1823 bool is_or = instr->opcode == aco_opcode::s_or_b64 || instr->opcode == aco_opcode::s_or_b32; in combine_constant_comparison_ordering()
2135 case aco_opcode::s_or_b64: in combine_salu_not_bitwise()
2161 case aco_opcode::s_or_b64: in combine_salu_not_bitwise()
2209 case aco_opcode::s_or_b64: in combine_salu_n2()
2890 instr->opcode == aco_opcode::s_and_b64 || instr->opcode == aco_opcode::s_or_b64) { in combine_instruction()
2920 case aco_opcode::s_or_b64: in to_uniform_bool_instr()
Daco_instruction_selection.cpp1294 …neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getT… in visit_alu_instr()
1296 bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz)); in visit_alu_instr()
1377 emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true); in visit_alu_instr()
2637 …tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTe… in visit_alu_instr()
8548 …Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc),… in build_cube_select()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td467 def S_OR_B64 : SOP2_64 <"s_or_b64",
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td251 defm S_OR_B64 : SOP2_64 <sop2<0x11, 0x0f>, "s_or_b64",