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Searched refs:s_sext_i32_i8 (Results 1 – 10 of 10) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dsext-in-reg.ll26 ; SI: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]]
62 ; SI: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]]
315 ; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
316 ; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
332 ; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
333 ; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
334 ; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
335 ; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
487 ; SI: s_sext_i32_i8 s{{[0-9]+}}, s{{[0-9]+}}
Dsmed3.ll381 ; GCN: s_sext_i32_i8
382 ; GCN: s_sext_i32_i8
383 ; GCN: s_sext_i32_i8
Dmin.ll61 ; SI: s_sext_i32_i8
62 ; SI: s_sext_i32_i8
Dsign_extend.ll67 ; GCN-DAG: s_sext_i32_i8 [[EXT0:s[0-9]+]], [[VAL]]
Dload-constant-i8.ll196 ; GCN-DAG: s_sext_i32_i8
232 ; GCN-DAG: s_sext_i32_i8
/external/llvm/test/MC/AMDGPU/
Dsop1.s139 s_sext_i32_i8 s1, s2 label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt96 # VI: s_sext_i32_i8 s1, s2 ; encoding: [0x02,0x16,0x81,0xbe]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td217 def S_SEXT_I32_I8 : SOP1_32 <"s_sext_i32_i8",
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td145 defm S_SEXT_I32_I8 : SOP1_32 <sop1<0x19, 0x16>, "s_sext_i32_i8",
/external/mesa3d/src/amd/compiler/
Daco_instruction_selection.cpp580 …bld.sop1(src_bits == 8 ? aco_opcode::s_sext_i32_i8 : aco_opcode::s_sext_i32_i16, Definition(tmp), … in convert_int()
643 bld.sop1(aco_opcode::s_sext_i32_i8, Definition(tmp), vec); in extract_8_16_bit_sgpr_element()