| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 268 .scalarize(0); in AMDGPULegalizerInfo()
273 .scalarize(0); in AMDGPULegalizerInfo()
281 .scalarize(0); in AMDGPULegalizerInfo()
286 .scalarize(0); in AMDGPULegalizerInfo()
296 .scalarize(0); in AMDGPULegalizerInfo()
302 .scalarize(0); // TODO: Implement. in AMDGPULegalizerInfo()
368 .scalarize(0); in AMDGPULegalizerInfo()
372 .scalarize(0); in AMDGPULegalizerInfo()
376 .scalarize(0); in AMDGPULegalizerInfo()
383 .scalarize(0) in AMDGPULegalizerInfo()
[all …]
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| /external/eigen/Eigen/src/Core/arch/SYCL/ |
| D | InteropHeaders.h | 134 EIGEN_DEVICE_FUNC static Scalar scalarize(Index, PacketReturnType &) { in scalarize() function
154 EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE static Scalar scalarize(Index index, PacketReturnType &in) {
186 EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE static Scalar scalarize(Index, PacketReturnType &in) {
203 EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE static Scalar scalarize(Index index, PacketReturnType &in) {
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64LegalizerInfo.cpp | 118 .scalarize(0); in AArch64LegalizerInfo()
178 .scalarize(0) in AArch64LegalizerInfo()
412 .scalarize(0); in AArch64LegalizerInfo()
494 scalarize(0)) in AArch64LegalizerInfo()
497 scalarize(1)) in AArch64LegalizerInfo()
538 .scalarize(0) in AArch64LegalizerInfo()
539 .scalarize(1); in AArch64LegalizerInfo()
580 .scalarize(1); in AArch64LegalizerInfo()
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| /external/llvm/test/CodeGen/X86/ |
| D | legalizedag_vec.ll | 7 ; legalizing the divide in LegalizeDAG, we scalarize the vector divide and make
|
| D | vec_shift6.ll | 6 ; Verify that we don't scalarize a packed vector shift left of 16-bit
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| D | nontemporal-2.ll | 1216 ; could even scalarize to movnti when we have 1-alignment: nontemporal is
|
| /external/llvm/test/Analysis/CostModel/AArch64/ |
| D | store.ll | 10 ; We scalarize the loads/stores because there is no vector register name for
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizeMutations.cpp | 67 LegalizeMutation LegalizeMutations::scalarize(unsigned TypeIdx) { in scalarize() function in LegalizeMutations
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| /external/llvm/test/Transforms/Scalarizer/ |
| D | store-bug.ll | 1 ; RUN: opt -scalarizer -scalarize-load-store -S < %s | FileCheck %s
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| D | dbginfo.ll | 1 ; RUN: opt %s -scalarizer -scalarize-load-store -S | FileCheck %s
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| D | basic.ll | 1 ; RUN: opt %s -scalarizer -scalarize-load-store -dce -S | FileCheck %s
|
| /external/llvm/test/Transforms/LoopVectorize/X86/ |
| D | fp32_to_uint32-cost-model.ll | 9 ; If we need to scalarize the fptoui and then use inserts to build up the
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| D | fp64_to_uint32-cost-model.ll | 10 ; If we need to scalarize the fptoui and then use inserts to build up the
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| /external/llvm/test/CodeGen/AArch64/ |
| D | aarch64-neon-v1i1-setcc.ll | 5 ; is illegal in AArch64 backend, the legalizer tries to scalarize this node.
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizerInfo.h | 286 LegalizeMutation scalarize(unsigned TypeIdx);
735 LegalizeRuleSet &scalarize(unsigned TypeIdx) { in scalarize() function
738 LegalizeMutations::scalarize(TypeIdx)); in scalarize()
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | vsx.ll | 1011 ; This should scalarize, and the current code quality is not good.
1025 ; This should scalarize, and the current code quality is not good.
1039 ; This should scalarize, and the current code quality is not good.
1129 ; This should scalarize, and the current code quality is not good.
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| /external/llvm/test/Transforms/LoopVectorize/ |
| D | induction.ll | 129 ; Make sure we scalarize the step vectors used for the pointer arithmetic. We
207 ; Make sure we scalarize the step vectors used for the pointer arithmetic. We
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| /external/eigen/unsupported/Eigen/CXX11/src/Tensor/ |
| D | TensorContractionSycl.h | 224 *ptr = PacketWrapper<PacketType, PacketSize>::scalarize(i, packet_data); in write()
695 …igen::TensorSycl::internal::PacketWrapper<PacketReturnType, PacketSize>::scalarize(mId, privetOut);
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| /external/llvm/docs/ |
| D | Passes.rst | 394 it refuses to scalarize aggregates which would require passing in more than
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| /external/mesa3d/docs/relnotes/ |
| D | 20.3.0.rst | 3440 - radeonsi: don't scalarize 16-bit vec2 ALU opcodes
4119 - nir: scalarize fdot in reverse
|