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/external/llvm/test/CodeGen/X86/
Dshift-bmi2.ll4 define i32 @shl32(i32 %x, i32 %shamt) nounwind uwtable readnone {
6 %shl = shl i32 %x, %shamt
28 define i32 @shl32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
31 %shl = shl i32 %x, %shamt
54 define i64 @shl64(i64 %x, i64 %shamt) nounwind uwtable readnone {
56 %shl = shl i64 %x, %shamt
72 define i64 @shl64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
75 %shl = shl i64 %x, %shamt
92 define i32 @lshr32(i32 %x, i32 %shamt) nounwind uwtable readnone {
94 %shl = lshr i32 %x, %shamt
[all …]
Dshift-and.ll12 %shamt = and i32 %t, 31
13 %res = shl i32 %val, %shamt
25 %shamt = and i32 %t, 63
26 %res = shl i32 %val, %shamt
40 %shamt = and i16 %t, 31
42 %tmp1 = ashr i16 %tmp, %shamt
51 %shamt = and i64 %t, 63
52 %res = lshr i64 %val, %shamt
60 %shamt = and i64 %t, 191
61 %res = lshr i64 %val, %shamt
Dvshift-4.ll10 %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
11 %shl = shl <2 x i64> %val, %shamt
26 %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
27 %shl = shl <2 x i64> %val, %shamt
36 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
37 %shl = shl <4 x i32> %val, %shamt
46 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
47 %shl = shl <4 x i32> %val, %shamt
56 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
57 %shl = shl <4 x i32> %val, %shamt
[all …]
Dvshift-5.ll12 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
13 %shl = shl <4 x i32> %val, %shamt
26 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
27 %shr = ashr <4 x i32> %val, %shamt
39 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
40 %shl = shl <4 x i32> %val, %shamt
52 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
53 %shr = ashr <4 x i32> %val, %shamt
/external/llvm/test/ExecutionEngine/OrcMCJIT/
Dtest-shift.ll4 %shamt = add i8 0, 1 ; <i8> [#uses=8]
5 %shift.upgrd.1 = zext i8 %shamt to i32 ; <i32> [#uses=1]
8 %shift.upgrd.2 = zext i8 %shamt to i32 ; <i32> [#uses=1]
13 %shift.upgrd.5 = zext i8 %shamt to i32 ; <i32> [#uses=1]
16 %shift.upgrd.6 = zext i8 %shamt to i32 ; <i32> [#uses=1]
20 %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1]
23 %shift.upgrd.8 = zext i8 %shamt to i64 ; <i64> [#uses=1]
26 %shift.upgrd.9 = zext i8 %shamt to i64 ; <i64> [#uses=1]
29 %shift.upgrd.10 = zext i8 %shamt to i64 ; <i64> [#uses=1]
/external/llvm/test/ExecutionEngine/MCJIT/
Dtest-shift.ll4 %shamt = add i8 0, 1 ; <i8> [#uses=8]
5 %shift.upgrd.1 = zext i8 %shamt to i32 ; <i32> [#uses=1]
8 %shift.upgrd.2 = zext i8 %shamt to i32 ; <i32> [#uses=1]
13 %shift.upgrd.5 = zext i8 %shamt to i32 ; <i32> [#uses=1]
16 %shift.upgrd.6 = zext i8 %shamt to i32 ; <i32> [#uses=1]
20 %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1]
23 %shift.upgrd.8 = zext i8 %shamt to i64 ; <i64> [#uses=1]
26 %shift.upgrd.9 = zext i8 %shamt to i64 ; <i64> [#uses=1]
29 %shift.upgrd.10 = zext i8 %shamt to i64 ; <i64> [#uses=1]
/external/llvm/test/ExecutionEngine/
Dtest-interp-vec-shift.ll4 %shamt = add <2 x i8> <i8 0, i8 0>, <i8 1, i8 2>
5 %shift.upgrd.1 = zext <2 x i8> %shamt to <2 x i32>
8 %shift.upgrd.2 = zext <2 x i8> %shamt to <2 x i32>
13 %shift.upgrd.5 = zext <2 x i8> %shamt to <2 x i32>
16 %shift.upgrd.6 = zext <2 x i8> %shamt to <2 x i32>
20 %shift.upgrd.7 = zext <2 x i8> %shamt to <2 x i64>
23 %shift.upgrd.8 = zext <2 x i8> %shamt to <2 x i64>
26 %shift.upgrd.9 = zext <2 x i8> %shamt to <2 x i64>
29 %shift.upgrd.10 = zext <2 x i8> %shamt to <2 x i64>
/external/llvm/test/CodeGen/PowerPC/
D2004-11-30-shr-var-crash.ll4 %shamt = add i8 0, 1 ; <i8> [#uses=1]
5 %shift.upgrd.1 = zext i8 %shamt to i64 ; <i64> [#uses=1]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td112 // TODO: should ensure invalid shamt is rejected when decoding.
330 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
331 "$rd, $rs1, $shamt">,
353 (ins GPR:$rs1, uimm5:$shamt), opcodestr,
354 "$rd, $rs1, $shamt">,
713 def : InstAlias<"sll $rd, $rs1, $shamt",
714 (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
715 def : InstAlias<"srl $rd, $rs1, $shamt",
716 (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
717 def : InstAlias<"sra $rd, $rs1, $shamt",
[all …]
DRISCVInstrFormats.td229 bits<6> shamt;
236 let Inst{25-20} = shamt;
246 bits<5> shamt;
253 let Inst{24-20} = shamt;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrShiftRotate.td847 (ins GR32:$src1, u8imm:$shamt), "",
848 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$shamt)))]>;
850 (ins GR64:$src1, u8imm:$shamt), "",
851 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$shamt)))]>;
854 (ins GR32:$src1, u8imm:$shamt), "",
855 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$shamt)))]>;
857 (ins GR64:$src1, u8imm:$shamt), "",
858 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$shamt)))]>;
862 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
867 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
[all …]
/external/swiftshader/third_party/astc-encoder/Source/
Dastc_color_unquantize.cpp443 int shamt = shamts[mode]; in hdr_rgbo_unpack3() local
444 red <<= shamt; in hdr_rgbo_unpack3()
445 green <<= shamt; in hdr_rgbo_unpack3()
446 blue <<= shamt; in hdr_rgbo_unpack3()
447 scale <<= shamt; in hdr_rgbo_unpack3()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstrFormats.td18 // shamt - only used on shift instructions, contains the shift amount.
148 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
158 bits<5> shamt;
167 let Inst{10-6} = shamt;
280 bits<5> shamt;
289 let Inst{10-6} = shamt;
DMicroMipsInstrFormats.td98 bits<3> shamt;
105 let Inst{3-1} = shamt;
364 bits<5> shamt;
371 let Inst{15-11} = shamt;
DMicroMipsInstrInfo.td332 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
333 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
797 (rotr GPR32Opnd:$rt, immZExt5:$shamt))];
1384 def : MipsInstAlias<"sll $rd, $shamt",
1385 (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1386 def : MipsInstAlias<"sra $rd, $shamt",
1387 (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1388 def : MipsInstAlias<"srl $rd, $shamt",
1389 (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
DMicroMips32r6InstrFormats.td530 bits<5> shamt;
537 let Inst{15-11} = shamt;
/external/llvm/lib/Target/Mips/
DMipsInstrFormats.td19 // shamt - only used on shift instructions, contains the shift amount.
145 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
155 bits<5> shamt;
164 let Inst{10-6} = shamt;
277 bits<5> shamt;
286 let Inst{10-6} = shamt;
DMicroMipsInstrInfo.td338 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
339 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
743 (rotr GPR32Opnd:$rt, immZExt5:$shamt))];
1095 def : MipsInstAlias<"sll $rd, $shamt",
1096 (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1097 def : MipsInstAlias<"sra $rd, $shamt",
1098 (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1099 def : MipsInstAlias<"srl $rd, $shamt",
1100 (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
DMicroMipsInstrFormats.td86 bits<3> shamt;
93 let Inst{3-1} = shamt;
352 bits<5> shamt;
359 let Inst{15-11} = shamt;
DMicroMips32r6InstrFormats.td610 bits<5> shamt;
617 let Inst{15-11} = shamt;
DMips64InstrInfo.td23 // shamt must fit in 6 bits.
330 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td852 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
857 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
904 def : Pat<(rotl GR32:$src, (i8 imm:$shamt)),
905 (RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>;
906 def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
907 (RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
910 def : Pat<(rotl (loadi32 addr:$src), (i8 imm:$shamt)),
911 (RORX32mi addr:$src, (ROT32L2R_imm8 imm:$shamt))>;
912 def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)),
913 (RORX64mi addr:$src, (ROT64L2R_imm8 imm:$shamt))>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/RISCV/
DRISCVGenCompressInstEmitter.inc1743 // slli $rd, $rs1, $shamt
1749 // Operand: shamt
1761 // srai $rd, $rs1, $shamt
1767 // Operand: shamt
1779 // srli $rd, $rs1, $shamt
1785 // Operand: shamt
DRISCVGenGlobalISel.inc9628 …edicate_uimmlog2xlen>>:$shamt) => (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:P…
9632 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
9645 …edicate_uimmlog2xlen>>:$shamt) => (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:P…
9649 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
9710 …edicate_uimmlog2xlen>>:$shamt) => (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:P…
9714 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
9796 …edicate_uimmlog2xlen>>:$shamt) => (SRLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:P…
9800 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
9813 …edicate_uimmlog2xlen>>:$shamt) => (SRLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:P…
9817 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
[all …]
DRISCVGenMCCodeEmitter.inc1342 // op: shamt
1362 // op: shamt

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