| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | AArch64TargetParser.def | 59 AARCH64_ARCH_EXT_NAME("sm4", AArch64::AEK_SM4, "+sm4", "-sm4")
73 AARCH64_ARCH_EXT_NAME("sve2-sm4", AArch64::AEK_SVE2SM4, "+sve2-sm4", "-sve2-sm4")
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| /external/cpu_features/test/ |
| D | cpuinfo_aarch64_test.cc | 50 EXPECT_FALSE(info.features.sm4); in TEST()
139 EXPECT_FALSE(info.features.sm4); in TEST()
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| /external/ms-tpm-20-ref/TPMCmd/tpm/include/ |
| D | CryptSym.h | 51 # define IF_IMPLEMENTED_SM4(op) op(SM4, sm4)
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| D | TpmTypes.h | 1681 TPMI_SM4_KEY_BITS sm4; member
1700 TPMI_ALG_SYM_MODE sm4; member
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| /external/cpu_features/include/ |
| D | cpuinfo_aarch64.h | 43 int sm4 : 1; // Hardware-accelerated SM4. member
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| /external/tpm2-tss/src/tss2-mu/ |
| D | tpmu-types.c | 487 TPM2_ALG_SM4, VAL, sm4, Tss2_MU_UINT16_Marshal,
492 TPM2_ALG_SM4, sm4, Tss2_MU_UINT16_Unmarshal,
498 TPM2_ALG_SM4, VAL, sm4, Tss2_MU_UINT16_Marshal,
502 TPM2_ALG_SM4, sm4, Tss2_MU_UINT16_Unmarshal,
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| /external/cpu_features/src/ |
| D | impl_aarch64_linux_or_android.c | 45 LINE(AARCH64_SM4, sm4, "sm4", AARCH64_HWCAP_SM4, 0) \
|
| /external/eigen/bench/ |
| D | sparse_product.cpp | 104 EigenSparseMatrix sm1(rows,cols), sm2(rows,cols), sm3(rows,cols), sm4(rows,cols); in main() local
|
| /external/tpm2-tss/include/tss2/ |
| D | tss2_tpm2_types.h | 1219 TPMI_SM4_KEY_BITS sm4; /* all symmetric algorithms */ member
1228 TPMI_ALG_SYM_MODE sm4; member
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64.td | 29 "sm4", "HasSM4", "true",
112 def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true",
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| D | AArch64InstrInfo.td | 84 AssemblerPredicate<"FeatureSM4", "sm4">;
118 AssemblerPredicate<"FeatureSVE2SM4", "sve2-sm4">;
|
| /external/eigen/doc/ |
| D | TutorialSparse.dox | 246 sm4 = sm1 + sm2 + sm3;
249 On the other hand, there is no restriction on the target matrix sm4.
|
| /external/ms-tpm-20-ref/TPMCmd/tpm/src/support/ |
| D | Marshal.c | 3086 return TPMI_SM4_KEY_BITS_Unmarshal((TPMI_SM4_KEY_BITS *)&(target->sm4), buffer, size); in TPMU_SYM_KEY_BITS_Unmarshal()
3115 return TPMI_SM4_KEY_BITS_Marshal((TPMI_SM4_KEY_BITS *)&(source->sm4), buffer, size); in TPMU_SYM_KEY_BITS_Marshal()
3146 … return TPMI_ALG_SYM_MODE_Unmarshal((TPMI_ALG_SYM_MODE *)&(target->sm4), buffer, size, 1); in TPMU_SYM_MODE_Unmarshal()
3175 return TPMI_ALG_SYM_MODE_Marshal((TPMI_ALG_SYM_MODE *)&(source->sm4), buffer, size); in TPMU_SYM_MODE_Marshal()
|
| /external/hyphenation-patterns/ga/ |
| D | hyph-ga.pat.txt | 488 .sm4
|
| /external/mesa3d/docs/relnotes/ |
| D | 7.10.rst | 2192 - d3d1x: s/tpf/sm4/g
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenSubtargetInfo.inc | 302 …{ "sm4", "Enable SM3 and SM4 support", AArch64::FeatureSM4, { { { 0x1000000000000ULL, 0x0ULL, 0x0U…
312 …{ "sve2-sm4", "Enable SM4 SVE2 instructions", AArch64::FeatureSVE2SM4, { { { 0x0ULL, 0x440000000UL…
|
| D | AArch64GenAsmMatcher.inc | 1238 case Feature_HasSM4Bit: return "sm4";
1254 case Feature_HasSVE2SM4Bit: return "sve2-sm4";
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| /external/ComputeLibrary/data/images/ |
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