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/external/llvm/test/CodeGen/AArch64/
Darm64-smaxv.ll5 ; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
9 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a1)
16 ; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v0
20 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a1)
32 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a1)
38 ; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v0
42 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a1)
49 ; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v0
53 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a1)
60 ; CHECK: smaxv.4s [[REGNUM:s[0-9]+]], v0
[all …]
Darm64-neon-across.ll47 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)
49 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)
51 declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)
57 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16>)
59 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8>)
167 ; CHECK: smaxv b{{[0-9]+}}, {{v[0-9]+}}.8b
169 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a)
170 %0 = trunc i32 %smaxv.i to i8
176 ; CHECK: smaxv h{{[0-9]+}}, {{v[0-9]+}}.4h
178 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a)
[all …]
Daarch64-minmaxv.ll7 ; CHECK: smaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
29 ; CHECK: smaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
48 ; CHECK: smaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
64 ; CHECK-NOT: smaxv
420 ; CHECK: smaxv {{h[0-9]+}}, [[V0]]
445 ; CHECK-NEXT: smaxv {{s[0-9]+}}, [[V0]]
/external/capstone/suite/MC/AArch64/
Dneon-across.s.cs12 0x20,0xa8,0x30,0x0e = smaxv b0, v1.8b
13 0x20,0xa8,0x30,0x4e = smaxv b0, v1.16b
14 0x20,0xa8,0x70,0x0e = smaxv h0, v1.4h
15 0x20,0xa8,0x70,0x4e = smaxv h0, v1.8h
16 0x20,0xa8,0xb0,0x4e = smaxv s0, v1.4s
/external/llvm/test/MC/AArch64/
Dneon-across.s33 smaxv b0, v1.8b
34 smaxv b0, v1.16b
35 smaxv h0, v1.4h
36 smaxv h0, v1.8h
37 smaxv s0, v1.4s
Dneon-diagnostics.s3773 smaxv s0, v1.2s
3795 smaxv d0, v1.2d define
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1457 __ smaxv(b4, v5.V16B()); in GenerateTestSequenceNEON() local
1458 __ smaxv(b23, v0.V8B()); in GenerateTestSequenceNEON() local
1459 __ smaxv(h6, v0.V4H()); in GenerateTestSequenceNEON() local
1460 __ smaxv(h24, v8.V8H()); in GenerateTestSequenceNEON() local
1461 __ smaxv(s3, v16.V4S()); in GenerateTestSequenceNEON() local
Dtest-cpu-features-aarch64.cc1670 TEST_NEON(smaxv_0, smaxv(b0, v1.V8B()))
1671 TEST_NEON(smaxv_1, smaxv(b0, v1.V16B()))
1672 TEST_NEON(smaxv_2, smaxv(h0, v1.V4H()))
1673 TEST_NEON(smaxv_3, smaxv(h0, v1.V8H()))
1674 TEST_NEON(smaxv_4, smaxv(s0, v1.V4S()))
Dtest-disasm-sve-aarch64.cc2923 COMPARE(smaxv(b9, p3, z1.VnB()), "smaxv b9, p3, z1.b"); in TEST()
2924 COMPARE(smaxv(h19, p2, z1.VnH()), "smaxv h19, p2, z1.h"); in TEST()
2925 COMPARE(smaxv(s29, p1, z1.VnS()), "smaxv s29, p1, z1.s"); in TEST()
2926 COMPARE(smaxv(d9, p0, z1.VnD()), "smaxv d9, p0, z1.d"); in TEST()
Dtest-simulator-aarch64.cc4903 DEFINE_TEST_NEON_ACROSS(smaxv, Basic) in DEFINE_TEST_NEON_2SAME_FP_FP16_SCALAR()
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1221 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b
1222 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b
1223 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h
1224 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h
1225 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s
Dlog-disasm1221 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b
1222 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b
1223 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h
1224 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h
1225 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s
Dlog-cpufeatures-custom1220 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b ### {NEON} ###
1221 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b ### {NEON} ###
1222 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h ### {NEON} ###
1223 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h ### {NEON} ###
1224 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s ### {NEON} ###
Dlog-cpufeatures1220 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b // Needs: NEON
1221 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b // Needs: NEON
1222 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h // Needs: NEON
1223 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h // Needs: NEON
1224 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s // Needs: NEON
Dlog-cpufeatures-colour1220 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b NEON
1221 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b NEON
1222 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h NEON
1223 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h NEON
1224 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s NEON
Dlog-all5422 0x~~~~~~~~~~~~~~~~ 4e30a8a4 smaxv b4, v5.16b
5424 0x~~~~~~~~~~~~~~~~ 0e30a817 smaxv b23, v0.8b
5426 0x~~~~~~~~~~~~~~~~ 0e70a806 smaxv h6, v0.4h
5428 0x~~~~~~~~~~~~~~~~ 4e70a918 smaxv h24, v8.8h
5430 0x~~~~~~~~~~~~~~~~ 4eb0aa03 smaxv s3, v16.4s
/external/capstone/arch/AArch64/
DAArch64MappingInsnOp.inc5233 { /* AArch64_SMAXVv16i8v, ARM64_INS_SMAXV: smaxv.16b $rd, $rn */
5237 { /* AArch64_SMAXVv4i16v, ARM64_INS_SMAXV: smaxv.4h $rd, $rn */
5241 { /* AArch64_SMAXVv4i32v, ARM64_INS_SMAXV: smaxv.4s $rd, $rn */
5245 { /* AArch64_SMAXVv8i16v, ARM64_INS_SMAXV: smaxv.8h $rd, $rn */
5249 { /* AArch64_SMAXVv8i8v, ARM64_INS_SMAXV: smaxv.8b $rd, $rn */
/external/vixl/src/aarch64/
Dsimulator-aarch64.h3523 LogicVRegister smaxv(VectorFormat vform,
4363 LogicVRegister smaxv(VectorFormat vform,
Dassembler-aarch64.h3038 void smaxv(const VRegister& vd, const VRegister& vn);
5294 void smaxv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
Dlogic-aarch64.cc1308 LogicVRegister Simulator::smaxv(VectorFormat vform, in smaxv() function in vixl::aarch64::Simulator
1324 LogicVRegister Simulator::smaxv(VectorFormat vform, in smaxv() function in vixl::aarch64::Simulator
Dmacro-assembler-aarch64.h2887 V(smaxv, Smaxv) \
5675 smaxv(vd, pg, zn); in Smaxv()
Dsimulator-aarch64.cc7659 smaxv(vf, rd, rn); in VisitNEONAcrossLanes()
11409 smaxv(vform, vd, pg, zn); in VisitSVEIntReduction()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12565 "smaxv\003smc\004smin\005sminp\005sminv\005smlal\006smlal2\006smlalb\006"
17356 …{ 4430 /* smaxv */, AArch64::SMAXV_VPZ_H, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1…
17357 …{ 4430 /* smaxv */, AArch64::SMAXVv8i16v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_F…
17358 …{ 4430 /* smaxv */, AArch64::SMAXVv4i16v, Convert__Reg1_0__VectorReg641_1, AMFBS_HasNEON, { MCK_FP…
17359 …{ 4430 /* smaxv */, AArch64::SMAXV_VPZ_S, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1…
17360 …{ 4430 /* smaxv */, AArch64::SMAXVv4i32v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_F…
17361 …{ 4430 /* smaxv */, AArch64::SMAXV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1…
17362 …{ 4430 /* smaxv */, AArch64::SMAXV_VPZ_B, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1…
17363 …{ 4430 /* smaxv */, AArch64::SMAXVv16i8v, Convert__Reg1_0__VectorReg1281_1, AMFBS_HasNEON, { MCK_F…
17364 …{ 4430 /* smaxv */, AArch64::SMAXVv8i8v, Convert__Reg1_0__VectorReg641_1, AMFBS_HasNEON, { MCK_FPR…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td124 defm SMAXV_VPZ : sve_int_reduce_1<0b000, "smaxv", AArch64smaxv_pred>;
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md4950 void smaxv(const VRegister& vd, const VRegister& vn)
10064 void smaxv(const VRegister& vd, const PRegister& pg, const ZRegister& zn)

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