Searched refs:sqdecd (Results 1 – 10 of 10) sorted by relevance
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64SVEInstrInfo.td | 887 defm SQDECD_XPiWdI : sve_int_pred_pattern_b_s32<0b11010, "sqdecd", int_aarch64_sve_sqdecd_n32>; 891 defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd", int_aarch64_sve_sqdecd_n64>; 908 defm SQDECD_ZPiI : sve_int_countvlv<0b11010, "sqdecd", ZPR64, int_aarch64_sve_sqdecd, nxv2i64>;
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/external/vixl/src/aarch64/ |
D | assembler-aarch64.h | 5348 void sqdecd(const Register& xd, 5355 void sqdecd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1); 5359 void sqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
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D | assembler-sve-aarch64.cc | 459 V(sqdecd, SQDECD_r_rs_x) \ 498 V(sqdecd, SQDECD) \ in VIXL_SVE_UQINC_UQDEC_LIST() 527 V(sqdecd, SQDEC, D) \
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D | macro-assembler-aarch64.h | 5718 sqdecd(xd, wn, pattern, multiplier); 5723 sqdecd(rdn, pattern, multiplier); 5728 sqdecd(zdn, pattern, multiplier);
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenAsmMatcher.inc | 12568 "sqadd\006sqcadd\006sqdecb\006sqdecd\006sqdech\006sqdecp\006sqdecw\007sq" 17532 …{ 4596 /* sqdecd */, AArch64::SQDECD_XPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_H… 17533 …{ 4596 /* sqdecd */, AArch64::SQDECD_ZPiI, Convert__SVEVectorDReg1_0__Tie0_1_1__imm_95_31__imm_95_… 17534 …{ 4596 /* sqdecd */, AArch64::SQDECD_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31_… 17535 …{ 4596 /* sqdecd */, AArch64::SQDECD_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1, AMF… 17536 …{ 4596 /* sqdecd */, AArch64::SQDECD_ZPiI, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPattern1_1__imm… 17537 …{ 4596 /* sqdecd */, AArch64::SQDECD_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern… 17538 …{ 4596 /* sqdecd */, AArch64::SQDECD_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3, A… 17539 …{ 4596 /* sqdecd */, AArch64::SQDECD_ZPiI, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPattern1_1__Imm… 17540 …{ 4596 /* sqdecd */, AArch64::SQDECD_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4,… [all …]
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D | AArch64GenAsmWriter.inc | 22620 /* 9780 */ "sqdecd $\x01\0" 22621 /* 9790 */ "sqdecd $\x01, $\xFF\x03\x0E\0" 22622 /* 9806 */ "sqdecd $\x01, $\xFF\x02\x35\0" 22623 /* 9822 */ "sqdecd $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0" 22624 /* 9844 */ "sqdecd $\xFF\x01\x10\0" 22625 /* 9856 */ "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0"
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D | AArch64GenAsmWriter1.inc | 23341 /* 9758 */ "sqdecd $\x01\0" 23342 /* 9768 */ "sqdecd $\x01, $\xFF\x03\x0E\0" 23343 /* 9784 */ "sqdecd $\x01, $\xFF\x02\x35\0" 23344 /* 9800 */ "sqdecd $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0" 23345 /* 9822 */ "sqdecd $\xFF\x01\x10\0" 23346 /* 9834 */ "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0"
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/external/vixl/test/aarch64/ |
D | test-api-movprfx-aarch64.cc | 1179 __ sqdecd(z16.VnD(), SVE_MUL3); in TEST() local 1570 __ sqdecd(z29.VnD(), SVE_MUL3); in TEST() local
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/external/vixl/doc/aarch64/ |
D | supported-instructions-aarch64.md | 10302 void sqdecd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 10309 void sqdecd(const Register& xd, 10319 void sqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1)
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/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
D | IntrinsicImpl.inc | 727 "llvm.aarch64.sve.sqdecd", 728 "llvm.aarch64.sve.sqdecd.n32", 729 "llvm.aarch64.sve.sqdecd.n64", 10860 47, // llvm.aarch64.sve.sqdecd 10861 47, // llvm.aarch64.sve.sqdecd.n32 10862 47, // llvm.aarch64.sve.sqdecd.n64
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