| /external/vixl/test/aarch64/ |
| D | test-disasm-sve-aarch64.cc | 2030 COMPARE(sqdecp(x12, p7.VnB(), w12), "sqdecp x12, p7.b, w12"); in TEST()
2031 COMPARE(sqdecp(x12, p7.VnH(), w12), "sqdecp x12, p7.h, w12"); in TEST()
2032 COMPARE(sqdecp(x12, p7.VnS(), w12), "sqdecp x12, p7.s, w12"); in TEST()
2033 COMPARE(sqdecp(x12, p7.VnD(), w12), "sqdecp x12, p7.d, w12"); in TEST()
2034 COMPARE(sqdecp(x30, p5.VnB()), "sqdecp x30, p5.b"); in TEST()
2035 COMPARE(sqdecp(x30, p5.VnH()), "sqdecp x30, p5.h"); in TEST()
2036 COMPARE(sqdecp(x30, p5.VnS()), "sqdecp x30, p5.s"); in TEST()
2037 COMPARE(sqdecp(x30, p5.VnD()), "sqdecp x30, p5.d"); in TEST()
2038 COMPARE(sqdecp(z13.VnH(), p1), "sqdecp z13.h, p1"); in TEST()
2039 COMPARE(sqdecp(z13.VnS(), p1), "sqdecp z13.s, p1"); in TEST()
[all …]
|
| D | test-api-movprfx-aarch64.cc | 1185 __ sqdecp(z7.VnS(), p2); in TEST() local
1576 __ sqdecp(z16.VnS(), p1); in TEST() local
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12568 "sqadd\006sqcadd\006sqdecb\006sqdecd\006sqdech\006sqdecp\006sqdecw\007sq"
17550 …{ 4610 /* sqdecp */, AArch64::SQDECP_XP_H, Convert__Reg1_0__SVEPredicateHReg1_1__Tie0_1_1, AMFBS_H…
17551 …{ 4610 /* sqdecp */, AArch64::SQDECP_XP_S, Convert__Reg1_0__SVEPredicateSReg1_1__Tie0_1_1, AMFBS_H…
17552 …{ 4610 /* sqdecp */, AArch64::SQDECP_XP_D, Convert__Reg1_0__SVEPredicateDReg1_1__Tie0_1_1, AMFBS_H…
17553 …{ 4610 /* sqdecp */, AArch64::SQDECP_XP_B, Convert__Reg1_0__SVEPredicateBReg1_1__Tie0_1_1, AMFBS_H…
17554 …{ 4610 /* sqdecp */, AArch64::SQDECP_ZP_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateHReg1_…
17555 …{ 4610 /* sqdecp */, AArch64::SQDECP_ZP_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateAnyReg…
17556 …{ 4610 /* sqdecp */, AArch64::SQDECP_ZP_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateSReg1_…
17557 …{ 4610 /* sqdecp */, AArch64::SQDECP_ZP_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateAnyReg…
17558 …{ 4610 /* sqdecp */, AArch64::SQDECP_ZP_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicateDReg1_…
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 917 defm SQDECP_XPWd : sve_int_count_r_s32<0b01000, "sqdecp", int_aarch64_sve_sqdecp_n32>;
918 defm SQDECP_XP : sve_int_count_r_x64<0b01010, "sqdecp", int_aarch64_sve_sqdecp_n64>;
926 defm SQDECP_ZP : sve_int_count_v<0b01000, "sqdecp", int_aarch64_sve_sqdecp>;
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 5377 void sqdecp(const Register& xd,
5382 void sqdecp(const Register& xdn, const PRegisterWithLaneSize& pg);
5385 void sqdecp(const ZRegister& zdn, const PRegister& pg);
|
| D | assembler-sve-aarch64.cc | 2072 void Assembler::sqdecp(const Register& xd, in sqdecp() function in vixl::aarch64::Assembler
2087 void Assembler::sqdecp(const Register& xdn, const PRegisterWithLaneSize& pg) { in sqdecp() function in vixl::aarch64::Assembler
2099 void Assembler::sqdecp(const ZRegister& zdn, const PRegister& pg) { in sqdecp() function in vixl::aarch64::Assembler
|
| D | macro-assembler-aarch64.h | 5753 sqdecp(xdn, pg, wdn); in Sqdecp()
5758 sqdecp(xdn, pg); in Sqdecp()
5765 sqdecp(zd, pg); in Sqdecp()
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 10350 void sqdecp(const Register& xd,
10359 void sqdecp(const Register& xdn, const PRegisterWithLaneSize& pg)
10366 void sqdecp(const ZRegister& zdn, const PRegister& pg)
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicImpl.inc | 733 "llvm.aarch64.sve.sqdecp",
734 "llvm.aarch64.sve.sqdecp.n32",
735 "llvm.aarch64.sve.sqdecp.n64",
10866 1, // llvm.aarch64.sve.sqdecp
10867 1, // llvm.aarch64.sve.sqdecp.n32
10868 1, // llvm.aarch64.sve.sqdecp.n64
|