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Searched refs:sqdmull (Results 1 – 25 of 44) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-scalar-by-elem-saturating-mul.s6 sqdmull s1, h1, v1.h[1]
7 sqdmull s8, h2, v5.h[2]
8 sqdmull s12, h17, v9.h[3]
9 sqdmull s31, h31, v15.h[7]
10 sqdmull d1, s1, v4.s[0] define
11 sqdmull d31, s31, v31.s[3]
12 sqdmull d9, s10, v15.s[0] define
Dneon-scalar-mul.s61 sqdmull s12, h22, h12
62 sqdmull d15, s22, s12
Dneon-2velem.s247 sqdmull v0.4s, v1.4h, v2.h[2]
248 sqdmull v0.2d, v1.2s, v2.s[2]
249 sqdmull v0.2d, v1.2s, v22.s[2]
Dneon-diagnostics.s2558 sqdmull v0.4s, v1.4s, v2.4h
2559 sqdmull v0.2d, v1.2d, v2.2s
2579 sqdmull v0.8h, v1.8b, v2.8b
3583 sqdmull v0.4h, v1.4h, v2.h[2]
3584 sqdmull v0.4s, v1.4h, v2.h[8]
3585 sqdmull v0.4s, v1.4h, v16.h[4]
3586 sqdmull v0.2s, v1.2s, v2.s[2]
3587 sqdmull v0.2d, v1.2s, v2.s[4]
3588 sqdmull v0.2d, v1.2s, v22.s[4]
4839 sqdmull s12, h22, s12
[all …]
Darm64-advsimd.s1147 sqdmull.h s0, h0, v0[7]
1148 sqdmull.s d0, s0, v0[3]
1165 ; CHECK: sqdmull.h s0, h0, v0[7] ; encoding: [0x00,0xb8,0x70,0x5f]
1166 ; CHECK: sqdmull.s d0, s0, v0[3] ; encoding: [0x00,0xb8,0xa0,0x5f]
1253 sqdmull.4s v0, v0, v0[0]
1255 sqdmull.2d v0, v0, v0[2]
1322 ; CHECK: sqdmull.4s v0, v0, v0[0] ; encoding: [0x00,0xb0,0x40,0x0f]
1324 ; CHECK: sqdmull.2d v0, v0, v0[2] ; encoding: [0x00,0xb8,0x80,0x0f]
1985 sqdmull s0, h0, h0
1986 sqdmull d0, s0, s0 define
[all …]
Dneon-3vdiff.s269 sqdmull v0.4s, v1.4h, v2.4h
270 sqdmull v0.2d, v1.2s, v2.2s
/external/capstone/suite/MC/AArch64/
Dneon-scalar-by-elem-saturating-mul.s.cs2 0x21,0xb0,0x51,0x5f = sqdmull s1, h1, v1.h[1]
3 0x48,0xb0,0x65,0x5f = sqdmull s8, h2, v5.h[2]
4 0x2c,0xb2,0x79,0x5f = sqdmull s12, h17, v9.h[3]
5 0xff,0xbb,0x7f,0x5f = sqdmull s31, h31, v15.h[7]
6 0x21,0xb0,0x84,0x5f = sqdmull d1, s1, v4.s[0]
7 0xff,0xbb,0xbf,0x5f = sqdmull d31, s31, v31.s[3]
8 0x49,0xb1,0x8f,0x5f = sqdmull d9, s10, v15.s[0]
Dneon-scalar-mul.s.cs12 0xcc,0xd2,0x6c,0x5e = sqdmull s12, h22, h12
13 0xcf,0xd2,0xac,0x5e = sqdmull d15, s22, s12
Dneon-2velem.s.cs96 0x20,0xb0,0x62,0x0f = sqdmull v0.4s, v1.4h, v2.h[2]
97 0x20,0xb8,0x82,0x0f = sqdmull v0.2d, v1.2s, v2.s[2]
98 0x20,0xb8,0x96,0x0f = sqdmull v0.2d, v1.2s, v22.s[2]
Dneon-3vdiff.s.cs94 0x20,0xd0,0x62,0x0e = sqdmull v0.4s, v1.4h, v2.4h
95 0x20,0xd0,0xa2,0x0e = sqdmull v0.2d, v1.2s, v2.2s
/external/llvm/test/CodeGen/AArch64/
Dmachine-copy-prop.ll32 …%sqdmull = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> <i16 1, i16 0, i16 0, i1…
33 …= tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> zeroinitializer, <4 x i32> %sqdmull)
85 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
Darm64-neon-2velem-high.ll115 …%vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
126 …%vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
139 …%vqdmull9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> …
150 …%vqdmull9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> …
273 …%vqdmlal15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
285 …%vqdmlal15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
299 …%vqdmlal9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> …
311 …%vqdmlal9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> …
435 …%vqdmlsl15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
447 …%vqdmlsl15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
[all …]
Darm64-vmul.ll68 ;CHECK: sqdmull.4s
71 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
77 ;CHECK: sqdmull.2d
80 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
91 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
102 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
107 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
108 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
309 %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
320 %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
[all …]
Darm64-detect-vec-redux.ll21 …%vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> undef, <2 x i32> unde…
39 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) #1
Darm64-neon-2velem.ll25 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
27 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
1157 …%vqdmlal2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %shuffl…
1168 …%vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %shuffl…
1180 …%vqdmlal2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i, <4 x i16>…
1192 …%vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i, <2 x i32>…
1203 …%vqdmlsl2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %shuffl…
1214 …%vqdmlsl2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %shuffl…
1226 …%vqdmlsl2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i, <4 x i16>…
1238 …%vqdmlsl2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i, <2 x i32>…
[all …]
Darm64-neon-3vdiff.ll5 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
9 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
1675 ; CHECK: sqdmull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
1677 %vqdmull2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %a, <4 x i16> %b)
1683 ; CHECK: sqdmull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1685 %vqdmull2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %a, <2 x i32> %b)
1693 %vqdmlal2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %c)
1702 %vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %c)
1711 %vqdmlsl2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %c)
1720 %vqdmlsl2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %c)
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1346 # CHECK: sqdmull v0.4s, v1.4h, v2.4h
1347 # CHECK: sqdmull v0.2d, v1.2s, v2.2s
1778 # CHECK: sqdmull s12, h22, h12
1779 # CHECK: sqdmull d15, s22, s12
2397 # CHECK: sqdmull s1, h1, v1.h[0]
2398 # CHECK: sqdmull s1, h1, v1.h[1]
2399 # CHECK: sqdmull s1, h1, v1.h[2]
2400 # CHECK: sqdmull s1, h1, v1.h[3]
2401 # CHECK: sqdmull s1, h1, v1.h[4]
2402 # CHECK: sqdmull s1, h1, v1.h[5]
[all …]
Darm64-advsimd.txt1612 # CHECK: sqdmull.h s0, h0, v0[7]
1613 # CHECK: sqdmull.s d0, s0, v0[3]
1738 # CHECK: sqdmull.4s v0, v0, v0[0]
1740 # CHECK: sqdmull.2d v0, v0, v0[2]
2291 # CHECK: sqdmull s0, h0, h0
2292 # CHECK: sqdmull d0, s0, s0
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1572 __ sqdmull(d25, s2, s26); in GenerateTestSequenceNEON() local
1573 __ sqdmull(d30, s14, v5.S(), 1); in GenerateTestSequenceNEON() local
1574 __ sqdmull(s29, h18, h11); in GenerateTestSequenceNEON() local
1575 __ sqdmull(s11, h13, v7.H(), 6); in GenerateTestSequenceNEON() local
1576 __ sqdmull(v23.V2D(), v9.V2S(), v8.V2S()); in GenerateTestSequenceNEON() local
1577 __ sqdmull(v18.V2D(), v29.V2S(), v4.S(), 1); in GenerateTestSequenceNEON() local
1578 __ sqdmull(v17.V4S(), v24.V4H(), v7.V4H()); in GenerateTestSequenceNEON() local
1579 __ sqdmull(v8.V4S(), v15.V4H(), v5.H(), 1); in GenerateTestSequenceNEON() local
Dtest-simulator-aarch64.cc4694 DEFINE_TEST_NEON_3DIFF_LONG_SD(sqdmull, Basic)
4712 DEFINE_TEST_NEON_3DIFF_SCALAR_LONG_SD(sqdmull, Basic)
4931 DEFINE_TEST_NEON_BYELEMENT_DIFF(sqdmull, Basic, Basic, Basic) in DEFINE_TEST_NEON_2SAME_FP_FP16_SCALAR()
4952 DEFINE_TEST_NEON_BYELEMENT_DIFF_SCALAR(sqdmull, Basic, Basic, Basic) in DEFINE_TEST_NEON_2SAME_FP_FP16_SCALAR()
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1336 0x~~~~~~~~~~~~~~~~ 5ebad059 sqdmull d25, s2, s26
1337 0x~~~~~~~~~~~~~~~~ 5fa5b1de sqdmull d30, s14, v5.s[1]
1338 0x~~~~~~~~~~~~~~~~ 5e6bd25d sqdmull s29, h18, h11
1339 0x~~~~~~~~~~~~~~~~ 5f67b9ab sqdmull s11, h13, v7.h[6]
1340 0x~~~~~~~~~~~~~~~~ 0ea8d137 sqdmull v23.2d, v9.2s, v8.2s
1341 0x~~~~~~~~~~~~~~~~ 0fa4b3b2 sqdmull v18.2d, v29.2s, v4.s[1]
1342 0x~~~~~~~~~~~~~~~~ 0e67d311 sqdmull v17.4s, v24.4h, v7.4h
1343 0x~~~~~~~~~~~~~~~~ 0f55b1e8 sqdmull v8.4s, v15.4h, v5.h[1]
Dlog-disasm1336 0x~~~~~~~~~~~~~~~~ 5ebad059 sqdmull d25, s2, s26
1337 0x~~~~~~~~~~~~~~~~ 5fa5b1de sqdmull d30, s14, v5.s[1]
1338 0x~~~~~~~~~~~~~~~~ 5e6bd25d sqdmull s29, h18, h11
1339 0x~~~~~~~~~~~~~~~~ 5f67b9ab sqdmull s11, h13, v7.h[6]
1340 0x~~~~~~~~~~~~~~~~ 0ea8d137 sqdmull v23.2d, v9.2s, v8.2s
1341 0x~~~~~~~~~~~~~~~~ 0fa4b3b2 sqdmull v18.2d, v29.2s, v4.s[1]
1342 0x~~~~~~~~~~~~~~~~ 0e67d311 sqdmull v17.4s, v24.4h, v7.4h
1343 0x~~~~~~~~~~~~~~~~ 0f55b1e8 sqdmull v8.4s, v15.4h, v5.h[1]
/external/vixl/src/aarch64/
Dsimulator-aarch64.cc2182 sqdmull(vform, zd, zn_b, zm_idx); in SimulateSVESaturatingIntMulLongIdx()
2185 sqdmull(vform, zd, zn_t, zm_idx); in SimulateSVESaturatingIntMulLongIdx()
2196 sqdmull(vform, zd, zn_b, zm_idx); in SimulateSVESaturatingIntMulLongIdx()
2199 sqdmull(vform, zd, zn_t, zm_idx); in SimulateSVESaturatingIntMulLongIdx()
2697 sqdmull(vform, zd, zn_b, zm_b); in SimulateSVEIntMulLongVec()
2700 sqdmull(vform, zd, zn_t, zm_t); in SimulateSVEIntMulLongVec()
7546 sqdmull(vf_l, rd, rn, rm); in VisitNEON3Different()
7724 sqdmull(vf, rd, rn, temp, is_2); in SimulateNEONMulByElementLong()
8703 sqdmull(vf, rd, rn, rm); in VisitNEONScalar3Diff()
8903 Op = &Simulator::sqdmull; in VisitNEONScalarByIndexedElement()
Dlogic-aarch64.cc807 LogicVRegister Simulator::sqdmull(VectorFormat vform, in sqdmull() function in vixl::aarch64::Simulator
815 return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmull()
3874 LogicVRegister product = sqdmull(vform, temp, src1, src2, is_2); in sqdmlal()
3893 LogicVRegister product = sqdmull(vform, temp, src1, src2, is_2); in sqdmlsl()
3906 LogicVRegister Simulator::sqdmull(VectorFormat vform, in sqdmull() function in vixl::aarch64::Simulator
3921 return sqdmull(vform, dst, src1, src2, /* is_2 = */ true); in sqdmull2()
/external/capstone/arch/AArch64/
DAArch64MappingInsnOp.inc5729 { /* AArch64_SQDMULLi16, ARM64_INS_SQDMULL: sqdmull $rd, $rn, $rm */
5733 { /* AArch64_SQDMULLi32, ARM64_INS_SQDMULL: sqdmull $rd, $rn, $rm */
5737 { /* AArch64_SQDMULLv1i32_indexed, ARM64_INS_SQDMULL: sqdmull.h $rd, $rn, $rm$idx */
5741 { /* AArch64_SQDMULLv1i64_indexed, ARM64_INS_SQDMULL: sqdmull.s $rd, $rn, $rm$idx */
5745 { /* AArch64_SQDMULLv2i32_indexed, ARM64_INS_SQDMULL: sqdmull.2d $rd, $rn, $rm$idx */
5749 { /* AArch64_SQDMULLv2i32_v2i64, ARM64_INS_SQDMULL: sqdmull.2d $rd, $rn, $rm */
5753 { /* AArch64_SQDMULLv4i16_indexed, ARM64_INS_SQDMULL: sqdmull.4s $rd, $rn, $rm$idx */
5757 { /* AArch64_SQDMULLv4i16_v4i32, ARM64_INS_SQDMULL: sqdmull.4s $rd, $rn, $rm */

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