Searched refs:sqincw (Results 1 – 10 of 10) sorted by relevance
876 defm SQINCW_XPiWdI : sve_int_pred_pattern_b_s32<0b10000, "sqincw", int_aarch64_sve_sqincw_n32>;880 defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw", int_aarch64_sve_sqincw_n64>;900 defm SQINCW_ZPiI : sve_int_countvlv<0b10000, "sqincw", ZPR32, int_aarch64_sve_sqincw, nxv4i32>;
5456 void sqincw(const Register& xd,5463 void sqincw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);5467 void sqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
462 V(sqincw, SQINCW_r_rs_x) \501 V(sqincw, SQINCW) \ in VIXL_SVE_UQINC_UQDEC_LIST()529 V(sqincw, SQINC, W) \
5865 sqincw(xd, wn, pattern, multiplier);5870 sqincw(rdn, pattern, multiplier);5875 sqincw(zdn, pattern, multiplier);
17702 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_H…17703 …{ 4785 /* sqincw */, AArch64::SQINCW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__imm_95_31__imm_95_…17704 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31_…17705 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1, AMF…17706 …{ 4785 /* sqincw */, AArch64::SQINCW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPattern1_1__imm…17707 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiWdI, Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern…17708 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3, A…17709 …{ 4785 /* sqincw */, AArch64::SQINCW_ZPiI, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPattern1_1__Imm…17710 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiWdI, Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4,…25075 …{ 4785 /* sqincw */, AArch64::SQINCW_XPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_H…[all …]
22654 /* 10314 */ "sqincw $\x01\0"22655 /* 10324 */ "sqincw $\x01, $\xFF\x03\x0E\0"22656 /* 10340 */ "sqincw $\x01, $\xFF\x02\x35\0"22657 /* 10356 */ "sqincw $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"22658 /* 10378 */ "sqincw $\xFF\x01\x0B\0"22659 /* 10390 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
23375 /* 10292 */ "sqincw $\x01\0"23376 /* 10302 */ "sqincw $\x01, $\xFF\x03\x0E\0"23377 /* 10318 */ "sqincw $\x01, $\xFF\x02\x35\0"23378 /* 10334 */ "sqincw $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"23379 /* 10356 */ "sqincw $\xFF\x01\x0B\0"23380 /* 10368 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
1200 __ sqincw(z29.VnS(), SVE_ALL); in TEST() local1591 __ sqincw(z10.VnS(), SVE_ALL); in TEST() local
10622 void sqincw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1)10629 void sqincw(const Register& xd,10639 void sqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1)
750 "llvm.aarch64.sve.sqincw",751 "llvm.aarch64.sve.sqincw.n32",752 "llvm.aarch64.sve.sqincw.n64",10883 47, // llvm.aarch64.sve.sqincw10884 47, // llvm.aarch64.sve.sqincw.n3210885 47, // llvm.aarch64.sve.sqincw.n64