| /external/llvm/test/MC/AArch64/ |
| D | armv8.1a-rdma.s | 7 sqrdmlsh v0.4h, v1.4h, v2.4h
9 sqrdmlsh v0.2s, v1.2s, v2.2s
11 sqrdmlsh v0.4s, v1.4s, v2.4s
13 sqrdmlsh v0.8h, v1.8h, v2.8h
24 sqrdmlsh v0.2h, v1.2h, v2.2h
26 sqrdmlsh v0.8s, v1.8s, v2.8s
28 sqrdmlsh v0.4s, v1.8h, v2.2s
68 sqrdmlsh h0, h1, h2
70 sqrdmlsh s0, s1, s2
78 sqrdmlsh v0.4h, v1.4h, v2.h[3]
[all …]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-rdma.txt | 4 [0x20,0x8c,0x02,0x2e] # sqrdmlsh v0.8b, v1.8b, v2.8b
6 [0x20,0x8c,0xc2,0x2e] # sqrdmlsh v0.1d, v1.1d, v2.1d
8 [0x20,0x8c,0x02,0x6e] # sqrdmlsh v0.16b, v1.16b, v2.16b
10 [0x20,0x8c,0xc2,0x6e] # sqrdmlsh v0.2d, v1.2d, v2.2d
29 [0x20,0x8c,0x02,0x7e] # sqrdmlsh b0, b1, b2
31 [0x20,0x8c,0xc2,0x7e] # sqrdmlsh d0, d1, d2
42 [0x20,0xf0,0x32,0x2f] # sqrdmlsh v0.8b, v1.8b, v2.b[3]
44 [0x20,0xf0,0xe2,0x2f] # sqrdmlsh v0.1d, v1.1d, v2.d[1]
46 [0x20,0xf0,0x32,0x6f] # sqrdmlsh v0.16b, v1.16b, v2.b[3]
48 [0x20,0xf8,0xe2,0x6f] # sqrdmlsh v0.2d, v1.2d, v2.d[3]
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-v8.1a.ll | 75 ; CHECK-V81a: sqrdmlsh v0.4h, v1.4h, v2.4h
76 ; CHECK-V81a-apple: sqrdmlsh.4h v0, v1, v2
85 ; CHECK-V81a: sqrdmlsh v0.8h, v1.8h, v2.8h
86 ; CHECK-V81a-apple: sqrdmlsh.8h v0, v1, v2
95 ; CHECK-V81a: sqrdmlsh v0.2s, v1.2s, v2.2s
96 ; CHECK-V81a-apple: sqrdmlsh.2s v0, v1, v2
105 ; CHECK-V81a: sqrdmlsh v0.4s, v1.4s, v2.4s
106 ; CHECK-V81a-apple: sqrdmlsh.4s v0, v1, v2
169 ; CHECK-V81a: sqrdmlsh v0.4h, v1.4h, v2.h[3]
170 ; CHECK-V81a-apple: sqrdmlsh.4h v0, v1, v2[3]
[all …]
|
| /external/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 2226 __ sqrdmlsh(z11.VnB(), z16.VnB(), z31.VnB()); in TEST() local
2229 __ sqrdmlsh(z11.VnH(), z16.VnH(), z1.VnH(), 0); in TEST() local
2232 __ sqrdmlsh(z11.VnS(), z16.VnS(), z1.VnS(), 0); in TEST() local
2235 __ sqrdmlsh(z11.VnD(), z16.VnD(), z1.VnD(), 0); in TEST() local
3060 __ sqrdmlsh(z11.VnB(), z16.VnB(), z31.VnB()); in TEST() local
3063 __ sqrdmlsh(z11.VnH(), z16.VnH(), z1.VnH(), 0); in TEST() local
3066 __ sqrdmlsh(z11.VnS(), z16.VnS(), z1.VnS(), 0); in TEST() local
3069 __ sqrdmlsh(z11.VnD(), z16.VnD(), z1.VnD(), 0); in TEST() local
3413 __ sqrdmlsh(z11.VnB(), z16.VnB(), z11.VnB()); in TEST() local
3416 __ sqrdmlsh(z11.VnH(), z11.VnH(), z1.VnH(), 0); in TEST() local
[all …]
|
| D | test-cpu-features-aarch64.cc | 3431 TEST_RDM_NEON(sqrdmlsh_0, sqrdmlsh(v0.V4H(), v1.V4H(), v2.H(), 5))
3432 TEST_RDM_NEON(sqrdmlsh_1, sqrdmlsh(v0.V8H(), v1.V8H(), v2.H(), 5))
3433 TEST_RDM_NEON(sqrdmlsh_2, sqrdmlsh(v0.V2S(), v1.V2S(), v2.S(), 2))
3434 TEST_RDM_NEON(sqrdmlsh_3, sqrdmlsh(v0.V4S(), v1.V4S(), v2.S(), 1))
3435 TEST_RDM_NEON(sqrdmlsh_4, sqrdmlsh(h0, h1, v2.H(), 6))
3436 TEST_RDM_NEON(sqrdmlsh_5, sqrdmlsh(s0, s1, v2.S(), 1))
3437 TEST_RDM_NEON(sqrdmlsh_6, sqrdmlsh(v0.V4H(), v1.V4H(), v2.V4H()))
3438 TEST_RDM_NEON(sqrdmlsh_7, sqrdmlsh(v0.V8H(), v1.V8H(), v2.V8H()))
3439 TEST_RDM_NEON(sqrdmlsh_8, sqrdmlsh(v0.V2S(), v1.V2S(), v2.V2S()))
3440 TEST_RDM_NEON(sqrdmlsh_9, sqrdmlsh(v0.V4S(), v1.V4S(), v2.V4S()))
[all …]
|
| D | test-simulator-aarch64.cc | 4614 DEFINE_TEST_NEON_3SAME_HS(sqrdmlsh, Basic)
4663 DEFINE_TEST_NEON_3SAME_SCALAR_HS(sqrdmlsh, Basic)
4935 DEFINE_TEST_NEON_BYELEMENT(sqrdmlsh, Basic, Basic, Basic) in DEFINE_TEST_NEON_2SAME_FP_FP16_SCALAR()
4956 DEFINE_TEST_NEON_BYELEMENT_SCALAR(sqrdmlsh, Basic, Basic, Basic) in DEFINE_TEST_NEON_2SAME_FP_FP16_SCALAR()
|
| D | test-disasm-sve-aarch64.cc | 6964 COMPARE(sqrdmlsh(z11.VnB(), z16.VnB(), z31.VnB()), in TEST()
6966 COMPARE(sqrdmlsh(z11.VnD(), z16.VnD(), z31.VnD()), in TEST()
6968 COMPARE(sqrdmlsh(z11.VnH(), z16.VnH(), z31.VnH()), in TEST()
6970 COMPARE(sqrdmlsh(z11.VnS(), z16.VnS(), z31.VnS()), in TEST()
6994 COMPARE(sqrdmlsh(z2.VnD(), z16.VnD(), z14.VnD(), 0), in TEST()
6996 COMPARE(sqrdmlsh(z23.VnH(), z13.VnH(), z6.VnH(), 5), in TEST()
6998 COMPARE(sqrdmlsh(z27.VnS(), z8.VnS(), z4.VnS(), 2), in TEST()
|
| /external/vixl/src/aarch64/ |
| D | macro-assembler-sve-aarch64.cc | 1835 V(Sqrdmlsh, sqrdmlsh, FourRegDestructiveHelper) \
1871 V(Sqrdmlsh, sqrdmlsh, FourRegOneImmDestructiveHelper) \
|
| D | assembler-aarch64.h | 3387 void sqrdmlsh(const VRegister& vd, const VRegister& vn, const VRegister& vm);
3422 void sqrdmlsh(const VRegister& vd,
6416 void sqrdmlsh(const ZRegister& zda,
6423 void sqrdmlsh(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm);
|
| D | simulator-aarch64.h | 3184 LogicVRegister sqrdmlsh(VectorFormat vform,
3991 LogicVRegister sqrdmlsh(VectorFormat vform,
|
| D | simulator-aarch64.cc | 2857 sqrdmlsh(vform, zda, zn, (index >= 0) ? zm_idx : zm); in SimulateSVESaturatingMulAddHigh()
7427 sqrdmlsh(vf, rd, rn, rm); in VisitNEON3SameExtra()
7898 sqrdmlsh(vform, rd, rn, rm, index); in VisitNEONByIndexedElement()
8878 sqrdmlsh(vf, rd, rn, rm); in VisitNEONScalar3SameExtra()
8924 Op = &Simulator::sqrdmlsh; in VisitNEONScalarByIndexedElement()
|
| D | logic-aarch64.cc | 873 LogicVRegister Simulator::sqrdmlsh(VectorFormat vform, in sqrdmlsh() function in vixl::aarch64::Simulator
880 return sqrdmlsh(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqrdmlsh()
4207 LogicVRegister Simulator::sqrdmlsh(VectorFormat vform, in sqrdmlsh() function in vixl::aarch64::Simulator
|
| D | assembler-aarch64.cc | 3815 void Assembler::sqrdmlsh(const VRegister& vd, in sqrdmlsh() function in vixl::aarch64::Assembler
4230 V(sqrdmlsh, NEON_SQRDMLSH_byelement)
|
| D | assembler-sve-aarch64.cc | 8375 void Assembler::sqrdmlsh(const ZRegister& zda, in sqrdmlsh() function in vixl::aarch64::Assembler
8397 void Assembler::sqrdmlsh(const ZRegister& zda, in sqrdmlsh() function in vixl::aarch64::Assembler
|
| D | macro-assembler-aarch64.h | 2767 V(sqrdmlsh, Sqrdmlsh) \
2957 V(sqrdmlsh, Sqrdmlsh) \
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12572 "qincw\005sqneg\tsqrdcmlah\010sqrdmlah\010sqrdmlsh\010sqrdmulh\006sqrshl"
17751 …{ 4817 /* sqrdmlsh */, AArch64::SQRDMLSHv1i16, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_Ha…
17752 …{ 4817 /* sqrdmlsh */, AArch64::SQRDMLSHv1i32, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_Ha…
17753 …{ 4817 /* sqrdmlsh */, AArch64::SQRDMLSH_ZZZ_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorHReg…
17754 …{ 4817 /* sqrdmlsh */, AArch64::SQRDMLSH_ZZZ_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg…
17755 …{ 4817 /* sqrdmlsh */, AArch64::SQRDMLSH_ZZZ_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg…
17756 …{ 4817 /* sqrdmlsh */, AArch64::SQRDMLSH_ZZZ_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEVectorBReg…
17757 …{ 4817 /* sqrdmlsh */, AArch64::SQRDMLSH_ZZZI_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorHRe…
17758 …{ 4817 /* sqrdmlsh */, AArch64::SQRDMLSH_ZZZI_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSRe…
17759 …{ 4817 /* sqrdmlsh */, AArch64::SQRDMLSH_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDRe…
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 1243 defm SQRDMLSH_ZZZI : sve2_int_mla_by_indexed_elem<0b10, 0b1, "sqrdmlsh">;
1247 defm SQRDMLSH_ZZZ : sve2_int_mla<0b1, "sqrdmlsh">;
|
| D | AArch64InstrInfo.td | 3932 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
4196 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;
5640 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 5251 void sqrdmlsh(const VRegister& vd,
5261 void sqrdmlsh(const VRegister& vd, const VRegister& vn, const VRegister& vm)
10691 void sqrdmlsh(const ZRegister& zda,
10701 void sqrdmlsh(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm)
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3027 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
3280 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;
4658 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",
|