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Searched refs:sqshlu (Results 1 – 25 of 39) sorted by relevance

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/external/capstone/suite/MC/AArch64/
Dneon-scalar-shift-imm.s.cs19 0x4f,0x66,0x0e,0x7f = sqshlu b15, b18, #6
20 0x33,0x66,0x16,0x7f = sqshlu h19, h17, #6
21 0xd0,0x65,0x39,0x7f = sqshlu s16, s14, #25
22 0xab,0x65,0x60,0x7f = sqshlu d11, d13, #32
Dneon-simd-shift.s.cs71 0x20,0x64,0x0b,0x2f = sqshlu v0.8b, v1.8b, #3
72 0x20,0x64,0x13,0x2f = sqshlu v0.4h, v1.4h, #3
73 0x20,0x64,0x23,0x2f = sqshlu v0.2s, v1.2s, #3
74 0x20,0x64,0x0b,0x6f = sqshlu v0.16b, v1.16b, #3
75 0x20,0x64,0x13,0x6f = sqshlu v0.8h, v1.8h, #3
76 0x20,0x64,0x23,0x6f = sqshlu v0.4s, v1.4s, #3
77 0x20,0x64,0x43,0x6f = sqshlu v0.2d, v1.2d, #3
/external/llvm/test/MC/AArch64/
Dneon-scalar-shift-imm.s97 sqshlu b15, b18, #6
98 sqshlu h19, h17, #6
99 sqshlu s16, s14, #25
100 sqshlu d11, d13, #32
Dneon-simd-shift.s201 sqshlu v0.8b, v1.8b, #3
202 sqshlu v0.4h, v1.4h, #3
203 sqshlu v0.2s, v1.2s, #3
204 sqshlu v0.16b, v1.16b, #3
205 sqshlu v0.8h, v1.8h, #3
206 sqshlu v0.4s, v1.4s, #3
207 sqshlu v0.2d, v1.2d, #3
Darm64-advsimd.s1360 sqshlu b0, b0, #1
1361 sqshlu h0, h0, #2
1362 sqshlu s0, s0, #3
1363 sqshlu d0, d0, #4 define
1409 ; CHECK: sqshlu b0, b0, #1 ; encoding: [0x00,0x64,0x09,0x7f]
1410 ; CHECK: sqshlu h0, h0, #2 ; encoding: [0x00,0x64,0x12,0x7f]
1411 ; CHECK: sqshlu s0, s0, #3 ; encoding: [0x00,0x64,0x23,0x7f]
1412 ; CHECK: sqshlu d0, d0, #4 ; encoding: [0x00,0x64,0x44,0x7f]
1498 sqshlu.8b v0, v0, #1
1499 sqshlu.16b v0, v0, #2
[all …]
Dneon-diagnostics.s1708 sqshlu v0.8b, v1.8h, #3
1709 sqshlu v0.4h, v1.4s, #3
1710 sqshlu v0.2s, v1.2d, #3
1711 sqshlu v0.16b, v1.16b, #8
1712 sqshlu v0.8h, v1.8h, #16
1713 sqshlu v0.4s, v1.4s, #32
1714 sqshlu v0.2d, v1.2d, #64
5053 sqshlu b15, b18, #99
5054 sqshlu h19, h17, #99
5055 sqshlu s16, s14, #99
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-vshift.ll555 ;CHECK: sqshlu.8b v0, {{v[0-9]+}}, #1
557 …%tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i…
563 ;CHECK: sqshlu.4h v0, {{v[0-9]+}}, #1
565 …%tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i…
571 ;CHECK: sqshlu.2s v0, {{v[0-9]+}}, #1
573 … %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
579 ;CHECK: sqshlu.16b v0, {{v[0-9]+}}, #1
581 …%tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 …
587 ;CHECK: sqshlu.8h v0, {{v[0-9]+}}, #1
589 …%tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i…
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt1815 # CHECK: sqshlu b0, b0, #0x1
1816 # CHECK: sqshlu h0, h0, #0x2
1817 # CHECK: sqshlu s0, s0, #0x3
1818 # CHECK: sqshlu d0, d0, #0x4
2073 # CHECK: sqshlu.8b v0, v0, #0x1
2074 # CHECK: sqshlu.16b v0, v0, #0x2
2075 # CHECK: sqshlu.4h v0, v0, #0x3
2076 # CHECK: sqshlu.8h v0, v0, #0x4
2077 # CHECK: sqshlu.2s v0, v0, #0x5
2078 # CHECK: sqshlu.4s v0, v0, #0x6
[all …]
Dneon-instructions.txt900 # CHECK: sqshlu v0.8b, v1.8b, #3
901 # CHECK: sqshlu v0.4h, v1.4h, #3
902 # CHECK: sqshlu v0.2s, v1.2s, #3
903 # CHECK: sqshlu v0.16b, v1.16b, #3
904 # CHECK: sqshlu v0.8h, v1.8h, #3
905 # CHECK: sqshlu v0.4s, v1.4s, #3
906 # CHECK: sqshlu v0.2d, v1.2d, #3
1894 # CHECK: sqshlu b15, b18, #6
1895 # CHECK: sqshlu h19, h17, #6
1896 # CHECK: sqshlu s16, s14, #25
[all …]
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1658 __ sqshlu(b13, b14, 6); in GenerateTestSequenceNEON() local
1659 __ sqshlu(d0, d16, 44); in GenerateTestSequenceNEON() local
1660 __ sqshlu(h5, h29, 15); in GenerateTestSequenceNEON() local
1661 __ sqshlu(s29, s8, 13); in GenerateTestSequenceNEON() local
1662 __ sqshlu(v27.V16B(), v20.V16B(), 2); in GenerateTestSequenceNEON() local
1663 __ sqshlu(v24.V2D(), v12.V2D(), 11); in GenerateTestSequenceNEON() local
1664 __ sqshlu(v12.V2S(), v19.V2S(), 22); in GenerateTestSequenceNEON() local
1665 __ sqshlu(v8.V4H(), v12.V4H(), 11); in GenerateTestSequenceNEON() local
1666 __ sqshlu(v18.V4S(), v3.V4S(), 8); in GenerateTestSequenceNEON() local
1667 __ sqshlu(v3.V8B(), v10.V8B(), 1); in GenerateTestSequenceNEON() local
[all …]
Dtest-cpu-features-aarch64.cc1855 TEST_NEON(sqshlu_0, sqshlu(v0.V8B(), v1.V8B(), 4))
1856 TEST_NEON(sqshlu_1, sqshlu(v0.V16B(), v1.V16B(), 7))
1857 TEST_NEON(sqshlu_2, sqshlu(v0.V4H(), v1.V4H(), 14))
1858 TEST_NEON(sqshlu_3, sqshlu(v0.V8H(), v1.V8H(), 15))
1859 TEST_NEON(sqshlu_4, sqshlu(v0.V2S(), v1.V2S(), 13))
1860 TEST_NEON(sqshlu_5, sqshlu(v0.V4S(), v1.V4S(), 6))
1861 TEST_NEON(sqshlu_6, sqshlu(v0.V2D(), v1.V2D(), 42))
1862 TEST_NEON(sqshlu_7, sqshlu(b0, b1, 3))
1863 TEST_NEON(sqshlu_8, sqshlu(h0, h1, 15))
1864 TEST_NEON(sqshlu_9, sqshlu(s0, s1, 21))
[all …]
Dtest-disasm-sve-aarch64.cc6520 COMPARE(sqshlu(z10.VnB(), p1.Merging(), z10.VnB(), 0), in TEST()
6522 COMPARE(sqshlu(z10.VnB(), p1.Merging(), z10.VnB(), 2), in TEST()
6524 COMPARE(sqshlu(z10.VnB(), p1.Merging(), z10.VnB(), 5), in TEST()
6526 COMPARE(sqshlu(z10.VnB(), p1.Merging(), z10.VnB(), 7), in TEST()
6528 COMPARE(sqshlu(z10.VnH(), p1.Merging(), z10.VnH(), 0), in TEST()
6530 COMPARE(sqshlu(z10.VnH(), p1.Merging(), z10.VnH(), 15), in TEST()
6532 COMPARE(sqshlu(z10.VnS(), p1.Merging(), z10.VnS(), 0), in TEST()
6534 COMPARE(sqshlu(z10.VnS(), p1.Merging(), z10.VnS(), 31), in TEST()
6536 COMPARE(sqshlu(z10.VnD(), p1.Merging(), z10.VnD(), 0), in TEST()
6538 COMPARE(sqshlu(z10.VnD(), p1.Merging(), z10.VnD(), 63), in TEST()
Dtest-simulator-aarch64.cc4748 DEFINE_TEST_NEON_2OPIMM(sqshlu, Basic, TypeWidthFromZero) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4780 DEFINE_TEST_NEON_2OPIMM_SCALAR(sqshlu, Basic, TypeWidthFromZero) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
Dtest-api-movprfx-aarch64.cc2253 __ sqshlu(z10.VnB(), p1.Merging(), z10.VnB(), 0); in TEST() local
3628 __ sqshlu(z10.VnB(), p1.Merging(), z10.VnB(), 0); in TEST() local
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1422 0x~~~~~~~~~~~~~~~~ 7f0e65cd sqshlu b13, b14, #6
1423 0x~~~~~~~~~~~~~~~~ 7f6c6600 sqshlu d0, d16, #44
1424 0x~~~~~~~~~~~~~~~~ 7f1f67a5 sqshlu h5, h29, #15
1425 0x~~~~~~~~~~~~~~~~ 7f2d651d sqshlu s29, s8, #13
1426 0x~~~~~~~~~~~~~~~~ 6f0a669b sqshlu v27.16b, v20.16b, #2
1427 0x~~~~~~~~~~~~~~~~ 6f4b6598 sqshlu v24.2d, v12.2d, #11
1428 0x~~~~~~~~~~~~~~~~ 2f36666c sqshlu v12.2s, v19.2s, #22
1429 0x~~~~~~~~~~~~~~~~ 2f1b6588 sqshlu v8.4h, v12.4h, #11
1430 0x~~~~~~~~~~~~~~~~ 6f286472 sqshlu v18.4s, v3.4s, #8
1431 0x~~~~~~~~~~~~~~~~ 2f096543 sqshlu v3.8b, v10.8b, #1
[all …]
Dlog-disasm1422 0x~~~~~~~~~~~~~~~~ 7f0e65cd sqshlu b13, b14, #6
1423 0x~~~~~~~~~~~~~~~~ 7f6c6600 sqshlu d0, d16, #44
1424 0x~~~~~~~~~~~~~~~~ 7f1f67a5 sqshlu h5, h29, #15
1425 0x~~~~~~~~~~~~~~~~ 7f2d651d sqshlu s29, s8, #13
1426 0x~~~~~~~~~~~~~~~~ 6f0a669b sqshlu v27.16b, v20.16b, #2
1427 0x~~~~~~~~~~~~~~~~ 6f4b6598 sqshlu v24.2d, v12.2d, #11
1428 0x~~~~~~~~~~~~~~~~ 2f36666c sqshlu v12.2s, v19.2s, #22
1429 0x~~~~~~~~~~~~~~~~ 2f1b6588 sqshlu v8.4h, v12.4h, #11
1430 0x~~~~~~~~~~~~~~~~ 6f286472 sqshlu v18.4s, v3.4s, #8
1431 0x~~~~~~~~~~~~~~~~ 2f096543 sqshlu v3.8b, v10.8b, #1
[all …]
Dlog-cpufeatures-custom1421 0x~~~~~~~~~~~~~~~~ 7f0e65cd sqshlu b13, b14, #6 ### {NEON} ###
1422 0x~~~~~~~~~~~~~~~~ 7f6c6600 sqshlu d0, d16, #44 ### {NEON} ###
1423 0x~~~~~~~~~~~~~~~~ 7f1f67a5 sqshlu h5, h29, #15 ### {NEON} ###
1424 0x~~~~~~~~~~~~~~~~ 7f2d651d sqshlu s29, s8, #13 ### {NEON} ###
1425 0x~~~~~~~~~~~~~~~~ 6f0a669b sqshlu v27.16b, v20.16b, #2 ### {NEON} ###
1426 0x~~~~~~~~~~~~~~~~ 6f4b6598 sqshlu v24.2d, v12.2d, #11 ### {NEON} ###
1427 0x~~~~~~~~~~~~~~~~ 2f36666c sqshlu v12.2s, v19.2s, #22 ### {NEON} ###
1428 0x~~~~~~~~~~~~~~~~ 2f1b6588 sqshlu v8.4h, v12.4h, #11 ### {NEON} ###
1429 0x~~~~~~~~~~~~~~~~ 6f286472 sqshlu v18.4s, v3.4s, #8 ### {NEON} ###
1430 0x~~~~~~~~~~~~~~~~ 2f096543 sqshlu v3.8b, v10.8b, #1 ### {NEON} ###
[all …]
Dlog-cpufeatures1421 0x~~~~~~~~~~~~~~~~ 7f0e65cd sqshlu b13, b14, #6 // Needs: NEON
1422 0x~~~~~~~~~~~~~~~~ 7f6c6600 sqshlu d0, d16, #44 // Needs: NEON
1423 0x~~~~~~~~~~~~~~~~ 7f1f67a5 sqshlu h5, h29, #15 // Needs: NEON
1424 0x~~~~~~~~~~~~~~~~ 7f2d651d sqshlu s29, s8, #13 // Needs: NEON
1425 0x~~~~~~~~~~~~~~~~ 6f0a669b sqshlu v27.16b, v20.16b, #2 // Needs: NEON
1426 0x~~~~~~~~~~~~~~~~ 6f4b6598 sqshlu v24.2d, v12.2d, #11 // Needs: NEON
1427 0x~~~~~~~~~~~~~~~~ 2f36666c sqshlu v12.2s, v19.2s, #22 // Needs: NEON
1428 0x~~~~~~~~~~~~~~~~ 2f1b6588 sqshlu v8.4h, v12.4h, #11 // Needs: NEON
1429 0x~~~~~~~~~~~~~~~~ 6f286472 sqshlu v18.4s, v3.4s, #8 // Needs: NEON
1430 0x~~~~~~~~~~~~~~~~ 2f096543 sqshlu v3.8b, v10.8b, #1 // Needs: NEON
[all …]
Dlog-cpufeatures-colour1421 0x~~~~~~~~~~~~~~~~ 7f0e65cd sqshlu b13, b14, #6 NEON
1422 0x~~~~~~~~~~~~~~~~ 7f6c6600 sqshlu d0, d16, #44 NEON
1423 0x~~~~~~~~~~~~~~~~ 7f1f67a5 sqshlu h5, h29, #15 NEON
1424 0x~~~~~~~~~~~~~~~~ 7f2d651d sqshlu s29, s8, #13 NEON
1425 0x~~~~~~~~~~~~~~~~ 6f0a669b sqshlu v27.16b, v20.16b, #2 NEON
1426 0x~~~~~~~~~~~~~~~~ 6f4b6598 sqshlu v24.2d, v12.2d, #11 NEON
1427 0x~~~~~~~~~~~~~~~~ 2f36666c sqshlu v12.2s, v19.2s, #22 NEON
1428 0x~~~~~~~~~~~~~~~~ 2f1b6588 sqshlu v8.4h, v12.4h, #11 NEON
1429 0x~~~~~~~~~~~~~~~~ 6f286472 sqshlu v18.4s, v3.4s, #8 NEON
1430 0x~~~~~~~~~~~~~~~~ 2f096543 sqshlu v3.8b, v10.8b, #1 NEON
[all …]
Dlog-all5824 0x~~~~~~~~~~~~~~~~ 7f0e65cd sqshlu b13, b14, #6
5826 0x~~~~~~~~~~~~~~~~ 7f6c6600 sqshlu d0, d16, #44
5828 0x~~~~~~~~~~~~~~~~ 7f1f67a5 sqshlu h5, h29, #15
5830 0x~~~~~~~~~~~~~~~~ 7f2d651d sqshlu s29, s8, #13
5832 0x~~~~~~~~~~~~~~~~ 6f0a669b sqshlu v27.16b, v20.16b, #2
5834 0x~~~~~~~~~~~~~~~~ 6f4b6598 sqshlu v24.2d, v12.2d, #11
5836 0x~~~~~~~~~~~~~~~~ 2f36666c sqshlu v12.2s, v19.2s, #22
5838 0x~~~~~~~~~~~~~~~~ 2f1b6588 sqshlu v8.4h, v12.4h, #11
5840 0x~~~~~~~~~~~~~~~~ 6f286472 sqshlu v18.4s, v3.4s, #8
5842 0x~~~~~~~~~~~~~~~~ 2f096543 sqshlu v3.8b, v10.8b, #1
[all …]
/external/capstone/arch/AArch64/
DAArch64MappingInsnOp.inc5985 { /* AArch64_SQSHLUb, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */
5989 { /* AArch64_SQSHLUd, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */
5993 { /* AArch64_SQSHLUh, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */
5997 { /* AArch64_SQSHLUs, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */
6001 { /* AArch64_SQSHLUv16i8_shift, ARM64_INS_SQSHLU: sqshlu.16b $rd, $rn, $imm */
6005 { /* AArch64_SQSHLUv2i32_shift, ARM64_INS_SQSHLU: sqshlu.2s $rd, $rn, $imm */
6009 { /* AArch64_SQSHLUv2i64_shift, ARM64_INS_SQSHLU: sqshlu.2d $rd, $rn, $imm */
6013 { /* AArch64_SQSHLUv4i16_shift, ARM64_INS_SQSHLU: sqshlu.4h $rd, $rn, $imm */
6017 { /* AArch64_SQSHLUv4i32_shift, ARM64_INS_SQSHLU: sqshlu.4s $rd, $rn, $imm */
6021 { /* AArch64_SQSHLUv8i16_shift, ARM64_INS_SQSHLU: sqshlu.8h $rd, $rn, $imm */
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12574 "sqrshrun2\tsqrshrunb\tsqrshrunt\005sqshl\006sqshlr\006sqshlu\006sqshrn\007"
17872 …{ 4937 /* sqshlu */, AArch64::SQSHLUh, Convert__Reg1_0__Reg1_1__Imm0_151_2, AMFBS_HasNEON, { MCK_F…
17873 …{ 4937 /* sqshlu */, AArch64::SQSHLUs, Convert__Reg1_0__Reg1_1__Imm0_311_2, AMFBS_HasNEON, { MCK_F…
17874 …{ 4937 /* sqshlu */, AArch64::SQSHLUd, Convert__Reg1_0__Reg1_1__Imm0_631_2, AMFBS_HasNEON, { MCK_F…
17875 …{ 4937 /* sqshlu */, AArch64::SQSHLUb, Convert__Reg1_0__Reg1_1__Imm0_71_2, AMFBS_HasNEON, { MCK_FP…
17876 …{ 4937 /* sqshlu */, AArch64::SQSHLUv16i8_shift, Convert__VectorReg1281_0__VectorReg1281_2__Imm0_7…
17877 …{ 4937 /* sqshlu */, AArch64::SQSHLUv2i64_shift, Convert__VectorReg1281_0__VectorReg1281_2__Imm0_6…
17878 …{ 4937 /* sqshlu */, AArch64::SQSHLUv4i32_shift, Convert__VectorReg1281_0__VectorReg1281_2__Imm0_3…
17879 …{ 4937 /* sqshlu */, AArch64::SQSHLUv8i16_shift, Convert__VectorReg1281_0__VectorReg1281_2__Imm0_1…
17880 …{ 4937 /* sqshlu */, AArch64::SQSHLUv2i32_shift, Convert__VectorReg641_0__VectorReg641_2__Imm0_311…
[all …]
/external/vixl/src/aarch64/
Dassembler-aarch64.h2969 void sqshlu(const VRegister& vd, const VRegister& vn, int shift);
6479 void sqshlu(const ZRegister& zd,
Dsimulator-aarch64.cc3378 sqshlu(vform, result, zdn, left_shift_dist); in Simulate_ZdnT_PgM_ZdnT_const()
9064 sqshlu(vf, rd, rn, left_shift); in VisitNEONScalarShiftImmediate()
9167 sqshlu(vf, rd, rn, left_shift); in VisitNEONShiftImmediate()
Dsimulator-aarch64.h3828 LogicVRegister sqshlu(VectorFormat vform,

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