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Searched refs:src1_sel (Results 1 – 21 of 21) sorted by relevance

/external/llvm/test/MC/AMDGPU/
Dvop_sdwa.s30 v_min_u32 v194, v13, v1 dst_sel:BYTE_3 dst_unused:UNUSED_SEXT src0_sel:BYTE_3 src1_sel:BYTE_2
34 v_min_u32 v255, v4, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:WORD_1
38 v_min_u32 v200, v200, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
42 v_min_u32 v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
77 v_min_f32 v0, v0, v0 clamp dst_sel:DWORD src1_sel:BYTE_2
81 v_and_b32 v0, v0, v0 dst_unused:UNUSED_PAD src1_sel:BYTE_2
101 v_add_f32 v0, -|v0|, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
105 v_min_f32 v0, abs(v0), -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
113 v_and_b32 v0, sext(v0), sext(v0) dst_unused:UNUSED_PAD src1_sel:BYTE_2
117 v_cmp_class_f32 vcc, -v1, sext(v2) src0_sel:BYTE_2 src1_sel:WORD_0
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/external/llvm/test/MC/Disassembler/AMDGPU/
Dsdwa_vi.txt12 # VI: v_min_u32_sdwa v194, v13, v1 dst_sel:BYTE_3 dst_unused:UNUSED_SEXT src0_sel:BYTE_3 src1_sel:B…
15 # VI: v_min_u32_sdwa v255, v4, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:WOR…
18 # VI: v_min_u32_sdwa v200, v200, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:D…
21 # VI: v_min_u32_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD …
42 # VI: v_add_f32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD …
45 …0, v0, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:BYTE_2 ; encoding…
48 # VI: v_and_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 …
51 …sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding:…
60 # VI: v_add_f32_sdwa v0, -|v0|, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BY…
63 # VI: v_min_f32_sdwa v0, |v0|, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYT…
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOP2Instructions.td307 src0_sel:$src0_sel, src1_sel:$src1_sel);
346 …WA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
347 …A9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
360 …$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
361 …$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
376 src0_sel:$src0_sel, src1_sel:$src1_sel);
395 …A = "$vdst, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
396 …9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
412 src0_sel:$src0_sel, src1_sel:$src1_sel);
DVOPCInstructions.td70 src0_sel:$src0_sel, src1_sel:$src1_sel);
73 let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
629 clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);
631 let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel";
643 src0_sel:$src0_sel, src1_sel:$src1_sel);
645 let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
DR600InstrFormats.td89 bits<9> src1_sel = src1{8-0};
95 let Word0{21-13} = src1_sel;
DVOPInstructions.td401 bits<3> src1_sel;
414 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0);
437 bits<3> src1_sel;
446 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0);
DSIInstrInfo.td1090 def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>;
1843 clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
1851 src0_sel:$src0_sel, src1_sel:$src1_sel),
1857 src0_sel:$src0_sel, src1_sel:$src1_sel))),
2013 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
2014 " $dst_sel $dst_unused $src0_sel $src1_sel"
2041 … " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
2042 out_mods#" $dst_sel $dst_unused $src0_sel $src1_sel"
DR600InstrInfo.cpp257 {R600::OpName::src1, R600::OpName::src1_sel}, in getSelIdx()
310 {R600::OpName::src1, R600::OpName::src1_sel}, in getSrcs()
1307 OPERAND_CASE(R600::OpName::src1_sel) in getSlotedOps()
1346 R600::OpName::src1_sel, in buildSlotOfVectorInstruction()
DSIPeepholeSDWA.cpp377 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
1115 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src1_sel) != -1); in convertToSDWA()
1116 MachineOperand *Src1Sel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
DEvergreenInstructions.td554 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
586 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
DR600Instructions.td150 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
190 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
/external/llvm/lib/Target/AMDGPU/
DVIInstrFormats.td239 bits<3> src1_sel;
253 let Inst{58-56} = src1_sel;
DR600InstrFormats.td80 bits<9> src1_sel = src1{8-0};
86 let Word0{21-13} = src1_sel;
DSIInstrInfo.td570 def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>;
1294 clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
1299 src0_sel:$src0_sel, src1_sel:$src1_sel)
1306 clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
1311 src0_sel:$src0_sel, src1_sel:$src1_sel)
1391 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
1392 " $dst_sel $dst_unused $src0_sel $src1_sel"
1573 clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);
1574 let AsmSDWA = " vcc, $src0_fmodifiers, $src1_imodifiers$clamp $src0_sel $src1_sel";
1614 src0_sel:$src0_sel, src1_sel:$src1_sel);
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DR600InstrInfo.cpp265 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel}, in getSelIdx()
318 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel}, in getSrcs()
1330 OPERAND_CASE(AMDGPU::OpName::src1_sel) in getSlotedOps()
1369 AMDGPU::OpName::src1_sel, in buildSlotOfVectorInstruction()
DEvergreenInstructions.td485 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
517 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
DR600Instructions.td140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
180 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
/external/mesa3d/src/freedreno/ir2/
Dinstr-a2xx.h174 uint8_t src1_sel : 1; member
Ddisasm-a2xx.c245 print_srcreg(alu->src1_reg, alu->src1_sel, alu->src1_swiz, in disasm_alu()
/external/mesa3d/src/gallium/drivers/freedreno/a2xx/
Dir2_assemble.c281 bc->alu.src1_sel = src1.type != IR2_SRC_CONST; in fill_instr()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_shader.c809 int src1_sel, unsigned src1_chan_val) in single_alu_op2() argument
823 alu.src[1].sel = src1_sel; in single_alu_op2()
824 if (src1_sel == V_SQ_ALU_SRC_LITERAL) in single_alu_op2()
846 alu.src[1].sel = src1_sel; in single_alu_op2()
847 if (src1_sel == V_SQ_ALU_SRC_LITERAL) in single_alu_op2()
865 int src1_sel, unsigned src1_chan_val, in single_alu_op3() argument
880 alu.src[1].sel = src1_sel; in single_alu_op3()
881 if (src1_sel == V_SQ_ALU_SRC_LITERAL) in single_alu_op3()
10995 int src1_sel, int src1_chan) in emit_u64add() argument
11013 alu.src[1].sel = src1_sel; in emit_u64add()
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