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/external/capstone/suite/MC/AArch64/
Dneon-rounding-shift.s.cs2 0x20,0x54,0x22,0x0e = srshl v0.8b, v1.8b, v2.8b
3 0x20,0x54,0x22,0x4e = srshl v0.16b, v1.16b, v2.16b
4 0x20,0x54,0x62,0x0e = srshl v0.4h, v1.4h, v2.4h
5 0x20,0x54,0x62,0x4e = srshl v0.8h, v1.8h, v2.8h
6 0x20,0x54,0xa2,0x0e = srshl v0.2s, v1.2s, v2.2s
7 0x20,0x54,0xa2,0x4e = srshl v0.4s, v1.4s, v2.4s
8 0x20,0x54,0xe2,0x4e = srshl v0.2d, v1.2d, v2.2d
Dneon-scalar-rounding-shift.s.cs2 0xf1,0x57,0xe8,0x5e = srshl d17, d31, d8
/external/llvm/test/MC/AArch64/
Dneon-rounding-shift.s9 srshl v0.8b, v1.8b, v2.8b
10 srshl v0.16b, v1.16b, v2.16b
11 srshl v0.4h, v1.4h, v2.4h
12 srshl v0.8h, v1.8h, v2.8h
13 srshl v0.2s, v1.2s, v2.2s
14 srshl v0.4s, v1.4s, v2.4s
15 srshl v0.2d, v1.2d, v2.2d
Dneon-scalar-rounding-shift.s7 srshl d17, d31, d8
Dneon-diagnostics.s943 srshl v0.8h, v15.8h, v16.16b
1008 srshl h0, h1, h2
Darm64-advsimd.s353 srshl.8b v0, v0, v0
424 ; CHECK: srshl.8b v0, v0, v0 ; encoding: [0x00,0x54,0x20,0x0e]
/external/libavc/common/armv8/
Dih264_weighted_pred_av8.s151 srshl v4.8h, v4.8h , v0.8h //rounds off the weighted samples from rows 1,2
152 srshl v6.8h, v6.8h , v0.8h //rounds off the weighted samples from rows 3,4
185 srshl v4.8h, v4.8h , v0.8h //rounds off the weighted samples from row 1
186 srshl v6.8h, v6.8h , v0.8h //rounds off the weighted samples from row 2
187 srshl v8.8h, v8.8h , v0.8h //rounds off the weighted samples from row 3
189 srshl v10.8h, v10.8h , v0.8h //rounds off the weighted samples from row 4
230 srshl v12.8h, v12.8h , v0.8h //rounds off the weighted samples from row 1L
232 srshl v14.8h, v14.8h , v0.8h //rounds off the weighted samples from row 1H
233 srshl v16.8h, v16.8h , v0.8h //rounds off the weighted samples from row 2L
235 srshl v18.8h, v18.8h , v0.8h //rounds off the weighted samples from row 2H
[all …]
Dih264_weighted_bi_pred_av8.s183 srshl v4.8h, v4.8h , v0.8h //rounds off the weighted samples from rows 1,2
184 srshl v8.8h, v8.8h , v0.8h //rounds off the weighted samples from rows 3,4
222 srshl v4.8h, v4.8h , v0.8h //rounds off the weighted samples from row 1
223 srshl v8.8h, v8.8h , v0.8h //rounds off the weighted samples from row 2
224 srshl v12.8h, v12.8h , v0.8h //rounds off the weighted samples from row 3
226 srshl v16.8h, v16.8h , v0.8h //rounds off the weighted samples from row 4
282 srshl v20.8h, v20.8h , v0.8h //rounds off the weighted samples from row 1L
285 srshl v4.8h, v4.8h , v0.8h //rounds off the weighted samples from row 1H
286 srshl v24.8h, v24.8h , v0.8h //rounds off the weighted samples from row 2L
288 srshl v8.8h, v8.8h , v0.8h //rounds off the weighted samples from row 2H
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-vshift.ll151 ;CHECK: srshl.8b
154 %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
160 ;CHECK: srshl.4h
163 %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
169 ;CHECK: srshl.2s
172 %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
205 ;CHECK: srshl.16b
208 %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
214 ;CHECK: srshl.8h
217 %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
[all …]
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1730 __ srshl(d2, d9, d26); in GenerateTestSequenceNEON() local
1731 __ srshl(v29.V16B(), v17.V16B(), v11.V16B()); in GenerateTestSequenceNEON() local
1732 __ srshl(v8.V2D(), v15.V2D(), v4.V2D()); in GenerateTestSequenceNEON() local
1733 __ srshl(v25.V2S(), v17.V2S(), v8.V2S()); in GenerateTestSequenceNEON() local
1734 __ srshl(v19.V4H(), v7.V4H(), v7.V4H()); in GenerateTestSequenceNEON() local
1735 __ srshl(v13.V4S(), v2.V4S(), v17.V4S()); in GenerateTestSequenceNEON() local
1736 __ srshl(v22.V8B(), v6.V8B(), v21.V8B()); in GenerateTestSequenceNEON() local
1737 __ srshl(v10.V8H(), v17.V8H(), v4.V8H()); in GenerateTestSequenceNEON() local
Dtest-cpu-features-aarch64.cc1949 TEST_NEON(srshl_0, srshl(v0.V8B(), v1.V8B(), v2.V8B()))
1950 TEST_NEON(srshl_1, srshl(v0.V16B(), v1.V16B(), v2.V16B()))
1951 TEST_NEON(srshl_2, srshl(v0.V4H(), v1.V4H(), v2.V4H()))
1952 TEST_NEON(srshl_3, srshl(v0.V8H(), v1.V8H(), v2.V8H()))
1953 TEST_NEON(srshl_4, srshl(v0.V2S(), v1.V2S(), v2.V2S()))
1954 TEST_NEON(srshl_5, srshl(v0.V4S(), v1.V4S(), v2.V4S()))
1955 TEST_NEON(srshl_6, srshl(v0.V2D(), v1.V2D(), v2.V2D()))
1956 TEST_NEON(srshl_7, srshl(d0, d1, d2))
Dtest-simulator-aarch64.cc4561 DEFINE_TEST_NEON_3SAME(srshl, Basic)
4642 DEFINE_TEST_NEON_3SAME_SCALAR_D(srshl, Basic)
Dtest-api-movprfx-aarch64.cc2265 __ srshl(z31.VnB(), p7.Merging(), z31.VnB(), z3.VnB()); in TEST() local
3446 __ srshl(z31.VnB(), p7.Merging(), z31.VnB(), z31.VnB()); in TEST() local
3640 __ srshl(z31.VnB(), p7.Merging(), z31.VnB(), z3.VnB()); in TEST() local
Dtest-disasm-sve-aarch64.cc6610 COMPARE(srshl(z31.VnB(), p7.Merging(), z31.VnB(), z3.VnB()), in TEST()
6612 COMPARE(srshl(z31.VnD(), p7.Merging(), z31.VnD(), z3.VnD()), in TEST()
6614 COMPARE(srshl(z31.VnH(), p7.Merging(), z31.VnH(), z3.VnH()), in TEST()
6616 COMPARE(srshl(z31.VnS(), p7.Merging(), z31.VnS(), z3.VnS()), in TEST()
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1494 0x~~~~~~~~~~~~~~~~ 5efa5522 srshl d2, d9, d26
1495 0x~~~~~~~~~~~~~~~~ 4e2b563d srshl v29.16b, v17.16b, v11.16b
1496 0x~~~~~~~~~~~~~~~~ 4ee455e8 srshl v8.2d, v15.2d, v4.2d
1497 0x~~~~~~~~~~~~~~~~ 0ea85639 srshl v25.2s, v17.2s, v8.2s
1498 0x~~~~~~~~~~~~~~~~ 0e6754f3 srshl v19.4h, v7.4h, v7.4h
1499 0x~~~~~~~~~~~~~~~~ 4eb1544d srshl v13.4s, v2.4s, v17.4s
1500 0x~~~~~~~~~~~~~~~~ 0e3554d6 srshl v22.8b, v6.8b, v21.8b
1501 0x~~~~~~~~~~~~~~~~ 4e64562a srshl v10.8h, v17.8h, v4.8h
Dlog-disasm1494 0x~~~~~~~~~~~~~~~~ 5efa5522 srshl d2, d9, d26
1495 0x~~~~~~~~~~~~~~~~ 4e2b563d srshl v29.16b, v17.16b, v11.16b
1496 0x~~~~~~~~~~~~~~~~ 4ee455e8 srshl v8.2d, v15.2d, v4.2d
1497 0x~~~~~~~~~~~~~~~~ 0ea85639 srshl v25.2s, v17.2s, v8.2s
1498 0x~~~~~~~~~~~~~~~~ 0e6754f3 srshl v19.4h, v7.4h, v7.4h
1499 0x~~~~~~~~~~~~~~~~ 4eb1544d srshl v13.4s, v2.4s, v17.4s
1500 0x~~~~~~~~~~~~~~~~ 0e3554d6 srshl v22.8b, v6.8b, v21.8b
1501 0x~~~~~~~~~~~~~~~~ 4e64562a srshl v10.8h, v17.8h, v4.8h
Dlog-cpufeatures-custom1493 0x~~~~~~~~~~~~~~~~ 5efa5522 srshl d2, d9, d26 ### {NEON} ###
1494 0x~~~~~~~~~~~~~~~~ 4e2b563d srshl v29.16b, v17.16b, v11.16b ### {NEON} ###
1495 0x~~~~~~~~~~~~~~~~ 4ee455e8 srshl v8.2d, v15.2d, v4.2d ### {NEON} ###
1496 0x~~~~~~~~~~~~~~~~ 0ea85639 srshl v25.2s, v17.2s, v8.2s ### {NEON} ###
1497 0x~~~~~~~~~~~~~~~~ 0e6754f3 srshl v19.4h, v7.4h, v7.4h ### {NEON} ###
1498 0x~~~~~~~~~~~~~~~~ 4eb1544d srshl v13.4s, v2.4s, v17.4s ### {NEON} ###
1499 0x~~~~~~~~~~~~~~~~ 0e3554d6 srshl v22.8b, v6.8b, v21.8b ### {NEON} ###
1500 0x~~~~~~~~~~~~~~~~ 4e64562a srshl v10.8h, v17.8h, v4.8h ### {NEON} ###
Dlog-cpufeatures1493 0x~~~~~~~~~~~~~~~~ 5efa5522 srshl d2, d9, d26 // Needs: NEON
1494 0x~~~~~~~~~~~~~~~~ 4e2b563d srshl v29.16b, v17.16b, v11.16b // Needs: NEON
1495 0x~~~~~~~~~~~~~~~~ 4ee455e8 srshl v8.2d, v15.2d, v4.2d // Needs: NEON
1496 0x~~~~~~~~~~~~~~~~ 0ea85639 srshl v25.2s, v17.2s, v8.2s // Needs: NEON
1497 0x~~~~~~~~~~~~~~~~ 0e6754f3 srshl v19.4h, v7.4h, v7.4h // Needs: NEON
1498 0x~~~~~~~~~~~~~~~~ 4eb1544d srshl v13.4s, v2.4s, v17.4s // Needs: NEON
1499 0x~~~~~~~~~~~~~~~~ 0e3554d6 srshl v22.8b, v6.8b, v21.8b // Needs: NEON
1500 0x~~~~~~~~~~~~~~~~ 4e64562a srshl v10.8h, v17.8h, v4.8h // Needs: NEON
Dlog-cpufeatures-colour1493 0x~~~~~~~~~~~~~~~~ 5efa5522 srshl d2, d9, d26 NEON
1494 0x~~~~~~~~~~~~~~~~ 4e2b563d srshl v29.16b, v17.16b, v11.16b NEON
1495 0x~~~~~~~~~~~~~~~~ 4ee455e8 srshl v8.2d, v15.2d, v4.2d NEON
1496 0x~~~~~~~~~~~~~~~~ 0ea85639 srshl v25.2s, v17.2s, v8.2s NEON
1497 0x~~~~~~~~~~~~~~~~ 0e6754f3 srshl v19.4h, v7.4h, v7.4h NEON
1498 0x~~~~~~~~~~~~~~~~ 4eb1544d srshl v13.4s, v2.4s, v17.4s NEON
1499 0x~~~~~~~~~~~~~~~~ 0e3554d6 srshl v22.8b, v6.8b, v21.8b NEON
1500 0x~~~~~~~~~~~~~~~~ 4e64562a srshl v10.8h, v17.8h, v4.8h NEON
Dlog-all5968 0x~~~~~~~~~~~~~~~~ 5efa5522 srshl d2, d9, d26
5970 0x~~~~~~~~~~~~~~~~ 4e2b563d srshl v29.16b, v17.16b, v11.16b
5972 0x~~~~~~~~~~~~~~~~ 4ee455e8 srshl v8.2d, v15.2d, v4.2d
5974 0x~~~~~~~~~~~~~~~~ 0ea85639 srshl v25.2s, v17.2s, v8.2s
5976 0x~~~~~~~~~~~~~~~~ 0e6754f3 srshl v19.4h, v7.4h, v7.4h
5978 0x~~~~~~~~~~~~~~~~ 4eb1544d srshl v13.4s, v2.4s, v17.4s
5980 0x~~~~~~~~~~~~~~~~ 0e3554d6 srshl v22.8b, v6.8b, v21.8b
5982 0x~~~~~~~~~~~~~~~~ 4e64562a srshl v10.8h, v17.8h, v4.8h
/external/capstone/arch/AArch64/
DAArch64MappingInsnOp.inc6361 { /* AArch64_SRSHLv16i8, ARM64_INS_SRSHL: srshl.16b $rd, $rn, $rm| */
6365 { /* AArch64_SRSHLv1i64, ARM64_INS_SRSHL: srshl $rd, $rn, $rm */
6369 { /* AArch64_SRSHLv2i32, ARM64_INS_SRSHL: srshl.2s $rd, $rn, $rm| */
6373 { /* AArch64_SRSHLv2i64, ARM64_INS_SRSHL: srshl.2d $rd, $rn, $rm| */
6377 { /* AArch64_SRSHLv4i16, ARM64_INS_SRSHL: srshl.4h $rd, $rn, $rm| */
6381 { /* AArch64_SRSHLv4i32, ARM64_INS_SRSHL: srshl.4s $rd, $rn, $rm| */
6385 { /* AArch64_SRSHLv8i16, ARM64_INS_SRSHL: srshl.8h $rd, $rn, $rm| */
6389 { /* AArch64_SRSHLv8i8, ARM64_INS_SRSHL: srshl.8b $rd, $rn, $rm| */
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt418 # CHECK: srshl v10.8b, v5.8b, v22.8b
420 # CHECK: srshl v1.4h, v5.4h, v31.4h
422 # CHECK: srshl v10.2s, v15.2s, v2.2s
474 # CHECK: srshl d16, d16, d16
/external/vixl/src/aarch64/
Dmacro-assembler-sve-aarch64.cc676 V(Srshl, srshl) \
Dassembler-aarch64.h2696 void srshl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
6530 void srshl(const ZRegister& zd,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12577 "un\007sqxtun2\007sqxtunb\007sqxtunt\006srhadd\003sri\005srshl\006srshlr"
17996 …{ 5092 /* srshl */, AArch64::SRSHLv1i64, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasNEON, { MCK_FPR…
17997 …{ 5092 /* srshl */, AArch64::SRSHLv16i8, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_…
17998 …{ 5092 /* srshl */, AArch64::SRSHLv2i64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_…
17999 …{ 5092 /* srshl */, AArch64::SRSHLv4i32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_…
18000 …{ 5092 /* srshl */, AArch64::SRSHLv8i16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_…
18001 …{ 5092 /* srshl */, AArch64::SRSHLv2i32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, …
18002 …{ 5092 /* srshl */, AArch64::SRSHLv4i16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, …
18003 …{ 5092 /* srshl */, AArch64::SRSHLv8i8, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4, A…
18004 …{ 5092 /* srshl */, AArch64::SRSHL_ZPmZ_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie…
[all …]

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