| /external/llvm/test/MC/AArch64/ |
| D | neon-3vdiff.s | 341 ssubw2 v0.8h, v1.8h, v2.16b
342 ssubw2 v0.4s, v1.4s, v2.8h
343 ssubw2 v0.2d, v1.2d, v2.4s
|
| D | neon-diagnostics.s | 2717 ssubw2 v0.8h, v1.8h, v2.16h
2718 ssubw2 v0.4s, v1.4s, v2.8s
2719 ssubw2 v0.2d, v1.2d, v2.4d
|
| /external/capstone/suite/MC/AArch64/ |
| D | neon-3vdiff.s.cs | 117 0x20,0x30,0x22,0x4e = ssubw2 v0.8h, v1.8h, v2.16b
118 0x20,0x30,0x62,0x4e = ssubw2 v0.4s, v1.4s, v2.8h
119 0x20,0x30,0xa2,0x4e = ssubw2 v0.2d, v1.2d, v2.4s
|
| /external/libavc/common/armv8/ |
| D | ih264_iquant_itrans_recon_av8.s | 675 ssubw2 v23.4s, v23.4s, v15.8h
684 ssubw2 v29.4s, v29.4s, v11.8h
688 ssubw2 v23.4s, v23.4s, v21.8h
697 ssubw2 v29.4s, v29.4s, v18.8h
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsub.ll | 313 ;CHECK: ssubw2.8h
326 ;CHECK: ssubw2.4s
339 ;CHECK: ssubw2.2d
|
| D | arm64-neon-3vdiff.ll | 487 ; CHECK: ssubw2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.16b
497 ; CHECK: ssubw2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.8h
507 ; CHECK: ssubw2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.4s
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 1405 # CHECK: ssubw2 v0.8h, v1.8h, v2.16b
1406 # CHECK: ssubw2 v0.4s, v1.4s, v2.8h
1407 # CHECK: ssubw2 v0.2d, v1.2d, v2.4s
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1793 __ ssubw2(v16.V2D(), v24.V2D(), v28.V4S()); in GenerateTestSequenceNEON() local
1794 __ ssubw2(v31.V4S(), v11.V4S(), v15.V8H()); in GenerateTestSequenceNEON() local
1795 __ ssubw2(v4.V8H(), v8.V8H(), v16.V16B()); in GenerateTestSequenceNEON() local
|
| D | test-cpu-features-aarch64.cc | 2012 TEST_NEON(ssubw2_0, ssubw2(v0.V8H(), v1.V8H(), v2.V16B()))
2013 TEST_NEON(ssubw2_1, ssubw2(v0.V4S(), v1.V4S(), v2.V8H()))
2014 TEST_NEON(ssubw2_2, ssubw2(v0.V2D(), v1.V2D(), v2.V4S()))
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 1557 0x~~~~~~~~~~~~~~~~ 4ebc3310 ssubw2 v16.2d, v24.2d, v28.4s
1558 0x~~~~~~~~~~~~~~~~ 4e6f317f ssubw2 v31.4s, v11.4s, v15.8h
1559 0x~~~~~~~~~~~~~~~~ 4e303104 ssubw2 v4.8h, v8.8h, v16.16b
|
| D | log-disasm | 1557 0x~~~~~~~~~~~~~~~~ 4ebc3310 ssubw2 v16.2d, v24.2d, v28.4s
1558 0x~~~~~~~~~~~~~~~~ 4e6f317f ssubw2 v31.4s, v11.4s, v15.8h
1559 0x~~~~~~~~~~~~~~~~ 4e303104 ssubw2 v4.8h, v8.8h, v16.16b
|
| D | log-cpufeatures-custom | 1556 0x~~~~~~~~~~~~~~~~ 4ebc3310 ssubw2 v16.2d, v24.2d, v28.4s ### {NEON} ###
1557 0x~~~~~~~~~~~~~~~~ 4e6f317f ssubw2 v31.4s, v11.4s, v15.8h ### {NEON} ###
1558 0x~~~~~~~~~~~~~~~~ 4e303104 ssubw2 v4.8h, v8.8h, v16.16b ### {NEON} ###
|
| D | log-cpufeatures | 1556 0x~~~~~~~~~~~~~~~~ 4ebc3310 ssubw2 v16.2d, v24.2d, v28.4s // Needs: NEON
1557 0x~~~~~~~~~~~~~~~~ 4e6f317f ssubw2 v31.4s, v11.4s, v15.8h // Needs: NEON
1558 0x~~~~~~~~~~~~~~~~ 4e303104 ssubw2 v4.8h, v8.8h, v16.16b // Needs: NEON
|
| D | log-cpufeatures-colour | 1556 0x~~~~~~~~~~~~~~~~ 4ebc3310 ssubw2 v16.2d, v24.2d, v28.4s [1;35mNEON[0;m
1557 0x~~~~~~~~~~~~~~~~ 4e6f317f ssubw2 v31.4s, v11.4s, v15.8h [1;35mNEON[0;m
1558 0x~~~~~~~~~~~~~~~~ 4e303104 ssubw2 v4.8h, v8.8h, v16.16b [1;35mNEON[0;m
|
| D | log-all | 6094 0x~~~~~~~~~~~~~~~~ 4ebc3310 ssubw2 v16.2d, v24.2d, v28.4s
6096 0x~~~~~~~~~~~~~~~~ 4e6f317f ssubw2 v31.4s, v11.4s, v15.8h
6098 0x~~~~~~~~~~~~~~~~ 4e303104 ssubw2 v4.8h, v8.8h, v16.16b
|
| /external/capstone/arch/AArch64/ |
| D | AArch64MappingInsnOp.inc | 6601 { /* AArch64_SSUBWv16i8_v8i16, ARM64_INS_SSUBW2: ssubw2.8h $rd, $rn, $rm */
6613 { /* AArch64_SSUBWv4i32_v2i64, ARM64_INS_SSUBW2: ssubw2.2d $rd, $rn, $rm */
6617 { /* AArch64_SSUBWv8i16_v4i32, ARM64_INS_SSUBW2: ssubw2.4s $rd, $rn, $rm */
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 3663 LogicVRegister ssubw2(VectorFormat vform,
|
| D | assembler-aarch64.h | 3154 void ssubw2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
|
| D | assembler-aarch64.cc | 2562 void Assembler::ssubw2(const VRegister& vd, in ssubw2() function in vixl::aarch64::Assembler
|
| D | logic-aarch64.cc | 3635 LogicVRegister Simulator::ssubw2(VectorFormat vform, in ssubw2() function in vixl::aarch64::Simulator
|
| D | macro-assembler-aarch64.h | 2777 V(ssubw2, Ssubw2) \
|
| D | simulator-aarch64.cc | 7573 ssubw2(vf_l, rd, rn, rm); in VisitNEON3Different()
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 5495 void ssubw2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12580 "ssubltb\005ssubw\006ssubw2\006ssubwb\006ssubwt\003st1\004st1b\004st1d\004"
18098 …{ 5213 /* ssubw2 */, AArch64::SSUBWv4i32_v2i64, Convert__VectorReg1281_0__VectorReg1281_2__VectorR…
18099 …{ 5213 /* ssubw2 */, AArch64::SSUBWv8i16_v4i32, Convert__VectorReg1281_0__VectorReg1281_2__VectorR…
18100 …{ 5213 /* ssubw2 */, AArch64::SSUBWv16i8_v8i16, Convert__VectorReg1281_0__VectorReg1281_2__VectorR…
25471 …{ 5213 /* ssubw2 */, AArch64::SSUBWv4i32_v2i64, Convert__VectorReg1281_1__VectorReg1281_2__VectorR…
25472 …{ 5213 /* ssubw2 */, AArch64::SSUBWv8i16_v4i32, Convert__VectorReg1281_1__VectorReg1281_2__VectorR…
25473 …{ 5213 /* ssubw2 */, AArch64::SSUBWv16i8_v8i16, Convert__VectorReg1281_1__VectorReg1281_2__VectorR…
|