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Searched refs:st4d (Results 1 – 15 of 15) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td679 defm ST4D_IMM : sve_mem_est_si<0b11, 0b11, ZZZZ_d, "st4d", simm4s4>;
693 def ST4D : sve_mem_est_ss<0b11, 0b11, ZZZZ_d, "st4d", GPR64NoXZRshifted64>;
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc5158 COMPARE(st4d(z0.VnD(), z1.VnD(), z2.VnD(), z3.VnD(), p0, SVEMemOperand(x19)), in TEST()
5160 COMPARE(st4d(z0.VnD(), in TEST()
5167 COMPARE(st4d(z0.VnD(), in TEST()
5351 COMPARE(st4d(z16.VnD(), in TEST()
5358 COMPARE(st4d(z16.VnD(), in TEST()
5365 COMPARE(st4d(z25.VnD(), in TEST()
Dtest-trace-aarch64.cc2852 __ st4d(z2.VnD(), in GenerateTestSequenceSVE() local
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12582 "t3b\004st3d\004st3h\004st3w\003st4\004st4b\004st4d\004st4h\004st4w\005s"
18702 …{ 5320 /* st4d */, AArch64::ST4D_IMM, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_…
18703 …{ 5320 /* st4d */, AArch64::ST4D, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__G…
18704 …{ 5320 /* st4d */, AArch64::ST4D_IMM, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_…
26075 …{ 5320 /* st4d */, AArch64::ST4D_IMM, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_…
26076 …{ 5320 /* st4d */, AArch64::ST4D, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__G…
26077 …{ 5320 /* st4d */, AArch64::ST4D_IMM, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_…
38649 { 5320 /* st4d */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
38650 { 5320 /* st4d */, 1 /* 0 */, MCK_SVEVectorList464, AMFBS_HasSVE },
38651 { 5320 /* st4d */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
[all …]
DAArch64GenAsmWriter.inc22745 /* 12203 */ "st4d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
DAArch64GenAsmWriter1.inc23466 /* 12181 */ "st4d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
/external/vixl/src/aarch64/
Dassembler-aarch64.h5575 void st4d(const ZRegister& zt1,
Dmacro-assembler-aarch64.h6007 st4d(zt1, zt2, zt3, zt4, pg, addr); in St4d()
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour2448 0x~~~~~~~~~~~~~~~~ e5e27002 st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3]
Dlog-disasm2448 0x~~~~~~~~~~~~~~~~ e5e27002 st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3]
Dlog-cpufeatures-custom2447 0x~~~~~~~~~~~~~~~~ e5e27002 st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3] ### {SVE} ###
Dlog-cpufeatures2447 0x~~~~~~~~~~~~~~~~ e5e27002 st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3] // Needs: SVE
Dlog-cpufeatures-colour2447 0x~~~~~~~~~~~~~~~~ e5e27002 st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3] SVE
Dlog-all11606 0x~~~~~~~~~~~~~~~~ e5e27002 st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3]
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md11155 void st4d(const ZRegister& zt1,