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Searched refs:st4h (Results 1 – 15 of 15) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td673 defm ST4H_IMM : sve_mem_est_si<0b01, 0b11, ZZZZ_h, "st4h", simm4s4>;
687 def ST4H : sve_mem_est_ss<0b01, 0b11, ZZZZ_h, "st4h", GPR64NoXZRshifted16>;
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc5118 COMPARE(st4h(z31.VnH(), z0.VnH(), z1.VnH(), z2.VnH(), p6, SVEMemOperand(x19)), in TEST()
5120 COMPARE(st4h(z15.VnH(), in TEST()
5127 COMPARE(st4h(z15.VnH(), in TEST()
5307 COMPARE(st4h(z31.VnH(), in TEST()
5314 COMPARE(st4h(z31.VnH(), in TEST()
5321 COMPARE(st4h(z31.VnH(), in TEST()
Dtest-trace-aarch64.cc2840 __ st4h(z0.VnH(), in GenerateTestSequenceSVE() local
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12582 "t3b\004st3d\004st3h\004st3w\003st4\004st4b\004st4d\004st4h\004st4w\005s"
18705 …{ 5325 /* st4h */, AArch64::ST4H_IMM, Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_…
18706 …{ 5325 /* st4h */, AArch64::ST4H, Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__G…
18707 …{ 5325 /* st4h */, AArch64::ST4H_IMM, Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_…
26078 …{ 5325 /* st4h */, AArch64::ST4H_IMM, Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_…
26079 …{ 5325 /* st4h */, AArch64::ST4H, Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__G…
26080 …{ 5325 /* st4h */, AArch64::ST4H_IMM, Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_…
38663 { 5325 /* st4h */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
38664 { 5325 /* st4h */, 1 /* 0 */, MCK_SVEVectorList416, AMFBS_HasSVE },
38665 { 5325 /* st4h */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
[all …]
DAArch64GenAsmWriter.inc22753 /* 12365 */ "st4h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
DAArch64GenAsmWriter1.inc23474 /* 12343 */ "st4h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
/external/vixl/src/aarch64/
Dassembler-aarch64.h5559 void st4h(const ZRegister& zt1,
Dmacro-assembler-aarch64.h5987 st4h(zt1, zt2, zt3, zt4, pg, addr); in St4h()
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour2446 0x~~~~~~~~~~~~~~~~ e4f1f000 st4h {z0.h, z1.h, z2.h, z3.h}, p4, [x0, #4, mul vl]
Dlog-disasm2446 0x~~~~~~~~~~~~~~~~ e4f1f000 st4h {z0.h, z1.h, z2.h, z3.h}, p4, [x0, #4, mul vl]
Dlog-cpufeatures-custom2445 0x~~~~~~~~~~~~~~~~ e4f1f000 st4h {z0.h, z1.h, z2.h, z3.h}, p4, [x0, #4, mul vl] ### {SVE} ###
Dlog-cpufeatures2445 0x~~~~~~~~~~~~~~~~ e4f1f000 st4h {z0.h, z1.h, z2.h, z3.h}, p4, [x0, #4, mul vl] // Needs: SVE
Dlog-cpufeatures-colour2445 0x~~~~~~~~~~~~~~~~ e4f1f000 st4h {z0.h, z1.h, z2.h, z3.h}, p4, [x0, #4, mul vl] SVE
Dlog-all11515 0x~~~~~~~~~~~~~~~~ e4f1f000 st4h {z0.h, z1.h, z2.h, z3.h}, p4, [x0, #4, mul vl]
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md11167 void st4h(const ZRegister& zt1,