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Searched refs:startBit (Results 1 – 20 of 20) sorted by relevance

/external/llvm/include/llvm/Support/
DEndian.h87 inline value_type readAtBitAlignment(const void *memory, uint64_t startBit) { in readAtBitAlignment() argument
88 assert(startBit < 8); in readAtBitAlignment()
89 if (startBit == 0) in readAtBitAlignment()
102 make_unsigned_t<value_type> lowerVal = val[0] >> startBit; in readAtBitAlignment()
105 (sizeof(value_type) * 8) - startBit; in readAtBitAlignment()
110 val[1] & (((make_unsigned_t<value_type>)1 << startBit) - 1); in readAtBitAlignment()
122 uint64_t startBit) { in writeAtBitAlignment() argument
123 assert(startBit < 8); in writeAtBitAlignment()
124 if (startBit == 0) in writeAtBitAlignment()
138 val[0] &= ((make_unsigned_t<value_type>)1 << startBit) - 1; in writeAtBitAlignment()
[all …]
/external/swiftshader/third_party/llvm-subzero/include/llvm/Support/
DEndian.h86 inline value_type readAtBitAlignment(const void *memory, uint64_t startBit) { in readAtBitAlignment() argument
87 assert(startBit < 8); in readAtBitAlignment()
88 if (startBit == 0) in readAtBitAlignment()
101 make_unsigned_t<value_type> lowerVal = val[0] >> startBit; in readAtBitAlignment()
104 (sizeof(value_type) * 8) - startBit; in readAtBitAlignment()
109 val[1] & (((make_unsigned_t<value_type>)1 << startBit) - 1); in readAtBitAlignment()
121 uint64_t startBit) { in writeAtBitAlignment() argument
122 assert(startBit < 8); in writeAtBitAlignment()
123 if (startBit == 0) in writeAtBitAlignment()
137 val[0] &= ((make_unsigned_t<value_type>)1 << startBit) - 1; in writeAtBitAlignment()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DEndian.h119 inline value_type readAtBitAlignment(const void *memory, uint64_t startBit) { in readAtBitAlignment() argument
120 assert(startBit < 8); in readAtBitAlignment()
121 if (startBit == 0) in readAtBitAlignment()
134 make_unsigned_t<value_type> lowerVal = val[0] >> startBit; in readAtBitAlignment()
137 (sizeof(value_type) * 8) - startBit; in readAtBitAlignment()
142 val[1] & (((make_unsigned_t<value_type>)1 << startBit) - 1); in readAtBitAlignment()
154 uint64_t startBit) { in writeAtBitAlignment() argument
155 assert(startBit < 8); in writeAtBitAlignment()
156 if (startBit == 0) in writeAtBitAlignment()
170 val[0] &= ((make_unsigned_t<value_type>)1 << startBit) - 1; in writeAtBitAlignment()
[all …]
/external/ppp/pppd/
Dpppcrypt.c57 Get7Bits(input, startBit) in Get7Bits() argument
59 int startBit;
63 word = (unsigned)input[startBit / 8] << 8;
64 word |= (unsigned)input[startBit / 8 + 1];
66 word >>= 15 - (startBit % 8 + 7);
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonShuffler.cpp173 static unsigned makeAllBits(unsigned startBit, unsigned Lanes) in makeAllBits() argument
176 startBit = (startBit << 1) | startBit; in makeAllBits()
177 return startBit; in makeAllBits()
/external/capstone/contrib/sysz_update/
D0004-capstone-generate-GenDisassemblerTables.inc.patch324 + << "static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \\\n"
330 + << " fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \\\n"
331 + << " return (insn & fieldMask) >> startBit; \\\n"
334 << "static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,\n"
338 << " fieldMask = (((InsnType)1 << numBits) - 1) << startBit;\n"
339 << " return (insn & fieldMask) >> startBit;\n"
/external/llvm/utils/TableGen/
DFixedLenDecoderEmitter.cpp256 Filter(FilterChooser &owner, unsigned startBit, unsigned numBits, bool mixed);
457 void runSingleFilter(unsigned startBit, unsigned numBit, bool mixed);
495 Filter::Filter(FilterChooser &owner, unsigned startBit, unsigned numBits, in Filter() argument
497 : Owner(&owner), StartBit(startBit), NumBits(numBits), Mixed(mixed) { in Filter()
1380 void FilterChooser::runSingleFilter(unsigned startBit, unsigned numBit, in runSingleFilter() argument
1383 Filters.emplace_back(*this, startBit, numBit, true); in runSingleFilter()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/RISCV/
DRISCVGenDisassemblerTables.inc34 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
36 assert(startBit + numBits <= 64 && "Cannot support >64-bit extractions!");
37 assert(startBit + numBits <= (sizeof(InsnType) * 8) &&
43 fieldMask = (((InsnType)1 << numBits) - 1) << startBit;
44 return (insn & fieldMask) >> startBit;
48 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
50 assert(startBit + numBits <= InsnType::max_size_in_bits && "Instruction field out of bounds!");
52 return (insn >> startBit) & fieldMask;
56 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
58 return fieldFromInstruction(insn, startBit, numBits, std::is_integral<InsnType>());
/external/capstone/arch/XCore/
DXCoreGenDisassemblerTables.inc17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
24 return (insn & fieldMask) >> startBit; \
/external/capstone/arch/TMS320C64x/
DTMS320C64xGenDisassemblerTables.inc14 static InsnType fname(InsnType insn, unsigned startBit, \
20 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
21 return (insn & fieldMask) >> startBit; \
/external/capstone/arch/Sparc/
DSparcGenDisassemblerTables.inc17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
24 return (insn & fieldMask) >> startBit; \
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenDisassemblerTables.inc34 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
36 assert(startBit + numBits <= 64 && "Cannot support >64-bit extractions!");
37 assert(startBit + numBits <= (sizeof(InsnType) * 8) &&
43 fieldMask = (((InsnType)1 << numBits) - 1) << startBit;
44 return (insn & fieldMask) >> startBit;
48 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
50 assert(startBit + numBits <= InsnType::max_size_in_bits && "Instruction field out of bounds!");
52 return (insn >> startBit) & fieldMask;
56 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
58 return fieldFromInstruction(insn, startBit, numBits, std::is_integral<InsnType>());
/external/capstone/arch/PowerPC/
DPPCGenDisassemblerTables.inc17 static InsnType fname(InsnType insn, unsigned startBit, \
24 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
25 return (insn & fieldMask) >> startBit; \
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenDisassemblerTables.inc34 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
36 assert(startBit + numBits <= 64 && "Cannot support >64-bit extractions!");
37 assert(startBit + numBits <= (sizeof(InsnType) * 8) &&
43 fieldMask = (((InsnType)1 << numBits) - 1) << startBit;
44 return (insn & fieldMask) >> startBit;
48 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
50 assert(startBit + numBits <= InsnType::max_size_in_bits && "Instruction field out of bounds!");
52 return (insn >> startBit) & fieldMask;
56 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
58 return fieldFromInstruction(insn, startBit, numBits, std::is_integral<InsnType>());
/external/capstone/arch/Mips/
DMipsGenDisassemblerTables.inc17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
24 return (insn & fieldMask) >> startBit; \
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDisassemblerTables.inc34 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
36 assert(startBit + numBits <= 64 && "Cannot support >64-bit extractions!");
37 assert(startBit + numBits <= (sizeof(InsnType) * 8) &&
43 fieldMask = (((InsnType)1 << numBits) - 1) << startBit;
44 return (insn & fieldMask) >> startBit;
48 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
50 assert(startBit + numBits <= InsnType::max_size_in_bits && "Instruction field out of bounds!");
52 return (insn >> startBit) & fieldMask;
56 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
58 return fieldFromInstruction(insn, startBit, numBits, std::is_integral<InsnType>());
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenDisassemblerTables.inc34 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
36 assert(startBit + numBits <= 64 && "Cannot support >64-bit extractions!");
37 assert(startBit + numBits <= (sizeof(InsnType) * 8) &&
43 fieldMask = (((InsnType)1 << numBits) - 1) << startBit;
44 return (insn & fieldMask) >> startBit;
48 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
50 assert(startBit + numBits <= InsnType::max_size_in_bits && "Instruction field out of bounds!");
52 return (insn >> startBit) & fieldMask;
56 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
58 return fieldFromInstruction(insn, startBit, numBits, std::is_integral<InsnType>());
/external/capstone/arch/SystemZ/
DSystemZGenDisassemblerTables.inc17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
24 return (insn & fieldMask) >> startBit; \
/external/capstone/arch/ARM/
DARMGenDisassemblerTables.inc17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
24 return (insn & fieldMask) >> startBit; \
/external/capstone/arch/AArch64/
DAArch64GenDisassemblerTables.inc17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
24 return (insn & fieldMask) >> startBit; \