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Searched refs:stencil_only_unrestricted_pipeline (Results 1 – 2 of 2) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_meta_clear.c372 state->clear[i].stencil_only_unrestricted_pipeline[j], in radv_device_finish_meta_clear_state()
778 &meta_state->clear[samples_log2].stencil_only_unrestricted_pipeline[index] : in pick_depthstencil_pipeline()
1430 &state->clear[i].stencil_only_unrestricted_pipeline[j], in radv_device_init_meta_clear_state()
Dradv_private.h497 VkPipeline stencil_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES]; member