| /external/llvm/test/CodeGen/ARM/ |
| D | ldaex-stlex.ll | 70 %res = call i32 @llvm.arm.stlex.p0i8(i32 %extval, i8* %addr)
79 %res = call i32 @llvm.arm.stlex.p0i16(i32 %extval, i16* %addr)
84 ; CHECK: stlex r0, r1, [r2]
86 %res = call i32 @llvm.arm.stlex.p0i32(i32 %val, i32* %addr)
90 declare i32 @llvm.arm.stlex.p0i8(i32, i8*) nounwind
91 declare i32 @llvm.arm.stlex.p0i16(i32, i16*) nounwind
92 declare i32 @llvm.arm.stlex.p0i32(i32, i32*) nounwind
|
| D | atomic-ops-v8.ll | 70 ; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
262 ; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
454 ; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
547 ; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r0, [r[[ADDR]]]
761 ; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]]
874 ; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]]
987 ; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]]
1116 ; CHECK: stlex [[STATUS:r[0-9]+]], r1, [r[[ADDR]]]
|
| /external/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8.s | 19 stlex r2, r1, [r7]
23 @ CHECK: stlex r2, r1, [r7] @ encoding: [0x91,0x2e,0x87,0xe1]
|
| D | load-store-acquire-release-v8-thumb.s | 19 stlex r2, r1, [r7]
23 @ CHECK: stlex r2, r1, [r7] @ encoding: [0xc7,0xe8,0xe2,0x1f]
|
| D | thumbv8m.s | 130 stlex r1, r2, [r3] label
|
| /external/capstone/suite/MC/ARM/ |
| D | load-store-acquire-release-v8-thumb.s.cs | 8 0xc7,0xe8,0xe2,0x1f = stlex r2, r1, [r7]
|
| D | load-store-acquire-release-v8.s.cs | 8 0x91,0x2e,0x87,0xe1 = stlex r2, r1, [r7]
|
| /external/llvm/test/Transforms/AtomicExpand/ARM/ |
| D | atomic-expansion-v8.ll | 30 ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* %ptr)
98 ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
136 ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* %ptr)
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8.txt | 17 # CHECK: stlex r2, r1, [r7] @ encoding: [0x91,0x2e,0x87,0xe1]
|
| D | load-store-acquire-release-v8-thumb.txt | 18 # CHECK: stlex r2, r1, [r7] @ encoding: [0xc7,0xe8,0xe2,0x1f]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3268 void stlex(Condition cond,
3272 void stlex(Register rd, Register rt, const MemOperand& operand) { in stlex() function
3273 stlex(al, rd, rt, operand); in stlex()
|
| D | disasm-aarch32.h | 1201 void stlex(Condition cond,
|
| D | disasm-aarch32.cc | 2966 void Disassembler::stlex(Condition cond, in stlex() function in vixl::aarch32::Disassembler
10114 stlex(CurrentCond(), in DecodeT32()
57460 stlex(condition, in DecodeA32()
|
| D | assembler-aarch32.cc | 10999 void Assembler::stlex(Condition cond, in stlex() function in vixl::aarch32::Assembler
11026 Delegate(kStlex, &Assembler::stlex, cond, rd, rt, operand); in stlex()
|
| D | macro-assembler-aarch32.h | 4218 stlex(cond, rd, rt, operand); in Stlex()
|
| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 940 { /* ARM_STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */
6154 { /* ARM_t2STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */
|
| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 940 { /* ARM_STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */
6154 { /* ARM_t2STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9908 "stc\004stc2\005stc2l\004stcl\003stl\004stlb\005stlex\006stlexb\006stlex"
11259 …{ 1483 /* stlex */, ARM::t2STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsTh…
11260 …{ 1483 /* stlex */, ARM::STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_…
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3413 "stlex", "\t$Rd, $Rt, $addr", "",
|
| D | ARMInstrInfo.td | 4742 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3636 "stlex", "\t$Rd, $Rt, $addr", "",
|
| D | ARMInstrInfo.td | 5086 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 690 arm_stlex, // llvm.arm.stlex
6748 "llvm.arm.stlex",
14688 3, // llvm.arm.stlex
|
| /external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/ |
| D | Intrinsics.gen | 690 arm_stlex, // llvm.arm.stlex
6748 "llvm.arm.stlex",
14688 3, // llvm.arm.stlex
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 690 arm_stlex, // llvm.arm.stlex
6748 "llvm.arm.stlex",
14688 3, // llvm.arm.stlex
|