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Searched refs:uqdech (Results 1 – 10 of 10) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td870 defm UQDECH_WPiI : sve_int_pred_pattern_b_u32<0b01011, "uqdech", int_aarch64_sve_uqdech_n32>;
874 defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech", int_aarch64_sve_uqdech_n64>;
897 defm UQDECH_ZPiI : sve_int_countvlv<0b01011, "uqdech", ZPR16, int_aarch64_sve_uqdech, nxv8i16>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12607 "umullb\006umullt\005uqadd\006uqdecb\006uqdecd\006uqdech\006uqdecp\006uq"
19584 …{ 6537 /* uqdech */, AArch64::UQDECH_WPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_H…
19585 …{ 6537 /* uqdech */, AArch64::UQDECH_XPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_H…
19586 …{ 6537 /* uqdech */, AArch64::UQDECH_ZPiI, Convert__SVEVectorHReg1_0__Tie0_1_1__imm_95_31__imm_95_…
19587 …{ 6537 /* uqdech */, AArch64::UQDECH_WPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1, AMF…
19588 …{ 6537 /* uqdech */, AArch64::UQDECH_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1, AMF…
19589 …{ 6537 /* uqdech */, AArch64::UQDECH_ZPiI, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPattern1_1__imm…
19590 …{ 6537 /* uqdech */, AArch64::UQDECH_WPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3, A…
19591 …{ 6537 /* uqdech */, AArch64::UQDECH_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3, A…
19592 …{ 6537 /* uqdech */, AArch64::UQDECH_ZPiI, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPattern1_1__Imm…
[all …]
DAArch64GenAsmWriter.inc22817 /* 13488 */ "uqdech $\x01\0"
22818 /* 13498 */ "uqdech $\x01, $\xFF\x03\x0E\0"
22819 /* 13514 */ "uqdech $\xFF\x01\x09\0"
22820 /* 13526 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0"
DAArch64GenAsmWriter1.inc23538 /* 13466 */ "uqdech $\x01\0"
23539 /* 13476 */ "uqdech $\x01, $\xFF\x03\x0E\0"
23540 /* 13492 */ "uqdech $\xFF\x01\x09\0"
23541 /* 13504 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0"
/external/vixl/src/aarch64/
Dassembler-aarch64.h5747 void uqdech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
5751 void uqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
Dassembler-sve-aarch64.cc477 V(uqdech, (rdn.IsX() ? UQDECH_r_rs_x : UQDECH_r_rs_uw)) \
531 V(uqdech, UQDEC, H) \
Dmacro-assembler-aarch64.h6158 uqdech(rdn, pattern, multiplier);
6163 uqdech(zdn, pattern, multiplier);
/external/vixl/test/aarch64/
Dtest-api-movprfx-aarch64.cc1233 __ uqdech(z24.VnH(), SVE_VL2); in TEST() local
1657 __ uqdech(z20.VnH(), SVE_VL2); in TEST() local
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md11807 void uqdech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1)
11814 void uqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1)
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc806 "llvm.aarch64.sve.uqdech",
807 "llvm.aarch64.sve.uqdech.n32",
808 "llvm.aarch64.sve.uqdech.n64",
10939 47, // llvm.aarch64.sve.uqdech
10940 47, // llvm.aarch64.sve.uqdech.n32
10941 47, // llvm.aarch64.sve.uqdech.n64