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/external/capstone/suite/MC/AArch64/
Dneon-scalar-shift-imm.s.cs28 0x4c,0x95,0x09,0x7f = uqshrn b12, h10, #7
29 0xca,0x95,0x1b,0x7f = uqshrn h10, s14, #5
30 0x8a,0x95,0x33,0x7f = uqshrn s10, d12, #13
Dneon-simd-shift.s.cs122 0x20,0x94,0x0d,0x2f = uqshrn v0.8b, v1.8h, #3
123 0x20,0x94,0x1d,0x2f = uqshrn v0.4h, v1.4s, #3
124 0x20,0x94,0x3d,0x2f = uqshrn v0.2s, v1.2d, #3
/external/llvm/test/MC/AArch64/
Dneon-scalar-shift-imm.s135 uqshrn b12, h10, #7
136 uqshrn h10, s14, #5
137 uqshrn s10, d12, #13
Dneon-simd-shift.s350 uqshrn v0.8b, v1.8h, #3
351 uqshrn v0.4h, v1.4s, #3
352 uqshrn v0.2s, v1.2d, #3
Darm64-advsimd.s1389 uqshrn b0, h0, #1
1390 uqshrn h0, s0, #2
1391 uqshrn s0, d0, #3
1438 ; CHECK: uqshrn b0, h0, #1 ; encoding: [0x00,0x94,0x0f,0x7f]
1439 ; CHECK: uqshrn h0, s0, #2 ; encoding: [0x00,0x94,0x1e,0x7f]
1440 ; CHECK: uqshrn s0, d0, #3 ; encoding: [0x00,0x94,0x3d,0x7f]
1582 uqshrn.8b v0, v0, #1
1584 uqshrn.4h v0, v0, #3
1586 uqshrn.2s v0, v0, #5
1754 ; CHECK: uqshrn.8b v0, v0, #1 ; encoding: [0x00,0x94,0x0f,0x2f]
[all …]
Dneon-diagnostics.s1952 uqshrn v0.8b, v1.8b, #3
1953 uqshrn v0.4h, v1.4h, #3
1954 uqshrn v0.2s, v1.2s, #3
5113 uqshrn b12, h10, #99
5114 uqshrn h10, s14, #99
5115 uqshrn s10, d12, #99
/external/llvm/test/CodeGen/AArch64/
Darm64-detect-vec-redux.ll9 …%vqshrn_n4 = tail call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> zeroinitializer, i32 19)
17 %vqshrn_n38 = tail call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %shuffle.i108, i32 1)
33 declare <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64>, i32) #1
36 declare <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16>, i32) #1
Darm64-neon-simd-shift.ll468 %vqshrn = tail call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %b, i32 3)
479 %vqshrn = tail call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %b, i32 9)
491 %vqshrn = tail call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %b, i32 19)
590 declare <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16>, i32)
592 declare <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32>, i32)
594 declare <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64>, i32)
Darm64-vshift.ll1074 ; CHECK: uqshrn {{s[0-9]+}}, d0, #1
1075 %tmp = call i32 @llvm.aarch64.neon.uqshrn.i32(i64 %A, i32 1)
1081 ;CHECK: uqshrn.8b v0, {{v[0-9]+}}, #1
1083 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)
1089 ;CHECK: uqshrn.4h v0, {{v[0-9]+}}, #1
1091 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)
1097 ;CHECK: uqshrn.2s v0, {{v[0-9]+}}, #1
1099 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)
1108 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)
1118 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt1842 # CHECK: uqshrn b0, h0, #0x7
1843 # CHECK: uqshrn h0, s0, #0xe
1844 # CHECK: uqshrn s0, d0, #0x1d
2157 # CHECK: uqshrn.8b v0, v0, #0x7
2159 # CHECK: uqshrn.4h v0, v0, #0xd
2161 # CHECK: uqshrn.2s v0, v0, #0x1b
Dneon-instructions.txt1034 # CHECK: uqshrn v0.8b, v1.8h, #3
1035 # CHECK: uqshrn v0.4h, v1.4s, #3
1036 # CHECK: uqshrn v0.2s, v1.2d, #3
1928 # CHECK: uqshrn b12, h10, #7
1929 # CHECK: uqshrn h10, s14, #5
1930 # CHECK: uqshrn s10, d12, #13
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2356 __ uqshrn(b21, h27, 7); in GenerateTestSequenceNEON() local
2357 __ uqshrn(h28, s26, 11); in GenerateTestSequenceNEON() local
2358 __ uqshrn(s13, d31, 17); in GenerateTestSequenceNEON() local
2359 __ uqshrn(v21.V2S(), v16.V2D(), 8); in GenerateTestSequenceNEON() local
2360 __ uqshrn(v24.V4H(), v24.V4S(), 2); in GenerateTestSequenceNEON() local
2361 __ uqshrn(v5.V8B(), v1.V8H(), 8); in GenerateTestSequenceNEON() local
Dtest-cpu-features-aarch64.cc2628 TEST_NEON(uqshrn_0, uqshrn(v0.V8B(), v1.V8H(), 6))
2629 TEST_NEON(uqshrn_1, uqshrn(v0.V4H(), v1.V4S(), 1))
2630 TEST_NEON(uqshrn_2, uqshrn(v0.V2S(), v1.V2D(), 7))
2634 TEST_NEON(uqshrn_3, uqshrn(b0, h1, 7))
2635 TEST_NEON(uqshrn_4, uqshrn(h0, s1, 11))
2636 TEST_NEON(uqshrn_5, uqshrn(s0, d1, 17))
Dtest-simulator-aarch64.cc4752 DEFINE_TEST_NEON_2OPIMM_NARROW(uqshrn, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4784 DEFINE_TEST_NEON_2OPIMM_SCALAR_NARROW(uqshrn, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour2011 0x~~~~~~~~~~~~~~~~ 7f099775 uqshrn b21, h27, #7
2012 0x~~~~~~~~~~~~~~~~ 7f15975c uqshrn h28, s26, #11
2013 0x~~~~~~~~~~~~~~~~ 7f2f97ed uqshrn s13, d31, #17
2014 0x~~~~~~~~~~~~~~~~ 2f389615 uqshrn v21.2s, v16.2d, #8
2015 0x~~~~~~~~~~~~~~~~ 2f1e9718 uqshrn v24.4h, v24.4s, #2
2016 0x~~~~~~~~~~~~~~~~ 2f089425 uqshrn v5.8b, v1.8h, #8
Dlog-disasm2011 0x~~~~~~~~~~~~~~~~ 7f099775 uqshrn b21, h27, #7
2012 0x~~~~~~~~~~~~~~~~ 7f15975c uqshrn h28, s26, #11
2013 0x~~~~~~~~~~~~~~~~ 7f2f97ed uqshrn s13, d31, #17
2014 0x~~~~~~~~~~~~~~~~ 2f389615 uqshrn v21.2s, v16.2d, #8
2015 0x~~~~~~~~~~~~~~~~ 2f1e9718 uqshrn v24.4h, v24.4s, #2
2016 0x~~~~~~~~~~~~~~~~ 2f089425 uqshrn v5.8b, v1.8h, #8
Dlog-cpufeatures-custom2010 0x~~~~~~~~~~~~~~~~ 7f099775 uqshrn b21, h27, #7 ### {NEON} ###
2011 0x~~~~~~~~~~~~~~~~ 7f15975c uqshrn h28, s26, #11 ### {NEON} ###
2012 0x~~~~~~~~~~~~~~~~ 7f2f97ed uqshrn s13, d31, #17 ### {NEON} ###
2013 0x~~~~~~~~~~~~~~~~ 2f389615 uqshrn v21.2s, v16.2d, #8 ### {NEON} ###
2014 0x~~~~~~~~~~~~~~~~ 2f1e9718 uqshrn v24.4h, v24.4s, #2 ### {NEON} ###
2015 0x~~~~~~~~~~~~~~~~ 2f089425 uqshrn v5.8b, v1.8h, #8 ### {NEON} ###
Dlog-cpufeatures2010 0x~~~~~~~~~~~~~~~~ 7f099775 uqshrn b21, h27, #7 // Needs: NEON
2011 0x~~~~~~~~~~~~~~~~ 7f15975c uqshrn h28, s26, #11 // Needs: NEON
2012 0x~~~~~~~~~~~~~~~~ 7f2f97ed uqshrn s13, d31, #17 // Needs: NEON
2013 0x~~~~~~~~~~~~~~~~ 2f389615 uqshrn v21.2s, v16.2d, #8 // Needs: NEON
2014 0x~~~~~~~~~~~~~~~~ 2f1e9718 uqshrn v24.4h, v24.4s, #2 // Needs: NEON
2015 0x~~~~~~~~~~~~~~~~ 2f089425 uqshrn v5.8b, v1.8h, #8 // Needs: NEON
Dlog-cpufeatures-colour2010 0x~~~~~~~~~~~~~~~~ 7f099775 uqshrn b21, h27, #7 NEON
2011 0x~~~~~~~~~~~~~~~~ 7f15975c uqshrn h28, s26, #11 NEON
2012 0x~~~~~~~~~~~~~~~~ 7f2f97ed uqshrn s13, d31, #17 NEON
2013 0x~~~~~~~~~~~~~~~~ 2f389615 uqshrn v21.2s, v16.2d, #8 NEON
2014 0x~~~~~~~~~~~~~~~~ 2f1e9718 uqshrn v24.4h, v24.4s, #2 NEON
2015 0x~~~~~~~~~~~~~~~~ 2f089425 uqshrn v5.8b, v1.8h, #8 NEON
Dlog-all9276 0x~~~~~~~~~~~~~~~~ 7f099775 uqshrn b21, h27, #7
9278 0x~~~~~~~~~~~~~~~~ 7f15975c uqshrn h28, s26, #11
9280 0x~~~~~~~~~~~~~~~~ 7f2f97ed uqshrn s13, d31, #17
9282 0x~~~~~~~~~~~~~~~~ 2f389615 uqshrn v21.2s, v16.2d, #8
9284 0x~~~~~~~~~~~~~~~~ 2f1e9718 uqshrn v24.4h, v24.4s, #2
9286 0x~~~~~~~~~~~~~~~~ 2f089425 uqshrn v5.8b, v1.8h, #8
/external/capstone/arch/AArch64/
DAArch64MappingInsnOp.inc8709 { /* AArch64_UQSHRNb, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */
8713 { /* AArch64_UQSHRNh, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */
8717 { /* AArch64_UQSHRNs, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */
8725 { /* AArch64_UQSHRNv2i32_shift, ARM64_INS_UQSHRN: uqshrn.2s $rd, $rn, $imm */
8729 { /* AArch64_UQSHRNv4i16_shift, ARM64_INS_UQSHRN: uqshrn.4h $rd, $rn, $imm */
8741 { /* AArch64_UQSHRNv8i8_shift, ARM64_INS_UQSHRN: uqshrn.8b $rd, $rn, $imm */
/external/vixl/src/aarch64/
Dsimulator-aarch64.cc2567 uqshrn(vform, result, zn, right_shift_dist); in SimulateSVENarrow()
9094 uqshrn(vf, rd, rn, right_shift); in VisitNEONScalarShiftImmediate()
9248 uqshrn(vf, rd, rn, right_shift); in VisitNEONShiftImmediate()
Dsimulator-aarch64.h3884 LogicVRegister uqshrn(VectorFormat vform,
Dassembler-aarch64.h3229 void uqshrn(const VRegister& vd, const VRegister& vn, int shift);
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td4738 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4794 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",

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