Home
last modified time | relevance | path

Searched refs:uqsub (Results 1 – 25 of 44) sorted by relevance

12

/external/llvm/test/CodeGen/AArch64/
Darm64-vqsub.ll32 ;CHECK: uqsub.8b
35 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
41 ;CHECK: uqsub.4h
44 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
50 ;CHECK: uqsub.2s
53 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
95 ;CHECK: uqsub.16b
98 %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
104 ;CHECK: uqsub.8h
107 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
[all …]
Darm64-arith-saturating.ll64 ; CHECK: uqsub s0, s0, s1
67 %vqsub.i = tail call i32 @llvm.aarch64.neon.uqsub.i32(i32 %vecext, i32 %vecext1) nounwind
73 ; CHECK: uqsub d0, d0, d1
76 %vqsub.i = tail call i64 @llvm.aarch64.neon.uqsub.i64(i64 %vecext, i64 %vecext1) nounwind
80 declare i64 @llvm.aarch64.neon.uqsub.i64(i64, i64) nounwind readnone
81 declare i32 @llvm.aarch64.neon.uqsub.i32(i32, i32) nounwind readnone
/external/llvm/test/MC/AArch64/
Dneon-saturating-add-sub.s66 uqsub v0.8b, v1.8b, v2.8b
67 uqsub v0.16b, v1.16b, v2.16b
68 uqsub v0.4h, v1.4h, v2.4h
69 uqsub v0.8h, v1.8h, v2.8h
70 uqsub v0.2s, v1.2s, v2.2s
71 uqsub v0.4s, v1.4s, v2.4s
72 uqsub v0.2d, v1.2d, v2.2d
Dneon-scalar-saturating-add-sub.s45 uqsub b0, b1, b2
46 uqsub h10, h11, h12
47 uqsub s20, s21, s2
48 uqsub d17, d31, d8
/external/capstone/suite/MC/AArch64/
Dneon-saturating-add-sub.s.cs23 0x20,0x2c,0x22,0x2e = uqsub v0.8b, v1.8b, v2.8b
24 0x20,0x2c,0x22,0x6e = uqsub v0.16b, v1.16b, v2.16b
25 0x20,0x2c,0x62,0x2e = uqsub v0.4h, v1.4h, v2.4h
26 0x20,0x2c,0x62,0x6e = uqsub v0.8h, v1.8h, v2.8h
27 0x20,0x2c,0xa2,0x2e = uqsub v0.2s, v1.2s, v2.2s
28 0x20,0x2c,0xa2,0x6e = uqsub v0.4s, v1.4s, v2.4s
29 0x20,0x2c,0xe2,0x6e = uqsub v0.2d, v1.2d, v2.2d
Dneon-scalar-saturating-add-sub.s.cs14 0x20,0x2c,0x22,0x7e = uqsub b0, b1, b2
15 0x6a,0x2d,0x6c,0x7e = uqsub h10, h11, h12
16 0xb4,0x2e,0xa2,0x7e = uqsub s20, s21, s2
17 0xf1,0x2f,0xe8,0x7e = uqsub d17, d31, d8
/external/renderscript-intrinsics-replacement-toolkit/renderscript-toolkit/src/main/cpp/
DYuvToRgb_advsimd.S110 …uqsub v0.8h, v0.8h, v29.8h // r0 = satu16(r0 - (16 * 149 + (128 >> 1) + 128 * 204) >>…
111 …uqsub v16.8h, v16.8h, v29.8h // r1 = satu16(r1 - (16 * 149 + (128 >> 1) + 128 * 204) >>…
112 uqsub v1.8h, v1.8h, v8.8h // g0 = satu16(g0 - g2)
113 uqsub v17.8h, v17.8h, v8.8h // g1 = satu16(g1 - g2)
114 …uqsub v2.8h, v2.8h, v31.8h // b0 = satu16(b0 - (16 * 149 + (128 << 2) + 128 * 254) >>…
115 …uqsub v18.8h, v18.8h, v31.8h // b1 = satu16(b1 - (16 * 149 + (128 << 2) + 128 * 254) >>…
117 …uqsub v4.8h, v4.8h, v29.8h // r0_hi = satu16(r0_hi - (16 * 149 + (128 >> 1) + 128 * 2…
118 …uqsub v20.8h, v20.8h, v29.8h // r1_hi = satu16(r1_hi - (16 * 149 + (128 >> 1) + 128 * 2…
119 uqsub v5.8h, v5.8h, v9.8h // g0_hi = satu16(g0_hi - g2_hi)
120 uqsub v21.8h, v21.8h, v9.8h // g1_hi = satu16(g1_hi - g2_hi)
[all …]
DBlend_advsimd.S410 uqsub v0.16b, v0.16b, v8.16b
411 uqsub v1.16b, v1.16b, v9.16b
412 uqsub v2.16b, v2.16b, v10.16b
413 uqsub v3.16b, v3.16b, v11.16b
/external/libhevc/common/arm64/
Dihevc_deblk_luma_horz.s207 uqsub v31.8b, v26.8b , v1.8b
224 uqsub v17.8b, v27.8b , v1.8b
245 uqsub v31.8b, v28.8b , v1.8b
293 uqsub v31.8b, v25.8b , v1.8b
301 uqsub v17.8b, v24.8b , v1.8b
399 uqsub v31.8b, v23.8b , v1.8b
Dihevc_deblk_luma_vert.s203 uqsub v30.8b,v7.8b,v19.8b
244 uqsub v31.8b,v5.8b,v19.8b
255 uqsub v25.8b,v4.8b,v19.8b
282 uqsub v31.8b,v2.8b,v19.8b
293 uqsub v28.8b,v3.8b,v19.8b
305 uqsub v31.8b,v6.8b,v19.8b
/external/libavc/common/armv8/
Dih264_deblk_chroma_av8.s401 uqsub v4.16b, v4.16b , v14.16b //Q2 = p0 - delta
403 uqsub v0.16b, v0.16b , v14.16b //Q0 = q0 - delta
555 uqsub v24.16b, v2.16b , v14.16b //p0-|delta|
556 uqsub v26.16b, v4.16b , v14.16b //q0-|delta|
Dih264_deblk_luma_av8.s181 uqsub v6.16b, v6.16b , v18.16b //Q3 = p0 - delta
185 uqsub v0.16b, v0.16b , v18.16b //Q0 = q0 - delta
627 uqsub v22.16b, v6.16b , v30.16b //clip(p0-delta)
641 uqsub v8.16b, v8.16b , v30.16b //clip(q0-delta)
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2365 __ uqsub(b28, b20, b26); in GenerateTestSequenceNEON() local
2366 __ uqsub(d0, d7, d10); in GenerateTestSequenceNEON() local
2367 __ uqsub(h26, h24, h7); in GenerateTestSequenceNEON() local
2368 __ uqsub(s23, s23, s16); in GenerateTestSequenceNEON() local
2369 __ uqsub(v14.V16B(), v16.V16B(), v24.V16B()); in GenerateTestSequenceNEON() local
2370 __ uqsub(v11.V2D(), v17.V2D(), v6.V2D()); in GenerateTestSequenceNEON() local
2371 __ uqsub(v10.V2S(), v10.V2S(), v8.V2S()); in GenerateTestSequenceNEON() local
2372 __ uqsub(v9.V4H(), v15.V4H(), v12.V4H()); in GenerateTestSequenceNEON() local
2373 __ uqsub(v23.V4S(), v18.V4S(), v7.V4S()); in GenerateTestSequenceNEON() local
2374 __ uqsub(v9.V8B(), v19.V8B(), v17.V8B()); in GenerateTestSequenceNEON() local
[all …]
Dtest-cpu-features-aarch64.cc2637 TEST_NEON(uqsub_0, uqsub(v0.V8B(), v1.V8B(), v2.V8B()))
2638 TEST_NEON(uqsub_1, uqsub(v0.V16B(), v1.V16B(), v2.V16B()))
2639 TEST_NEON(uqsub_2, uqsub(v0.V4H(), v1.V4H(), v2.V4H()))
2640 TEST_NEON(uqsub_3, uqsub(v0.V8H(), v1.V8H(), v2.V8H()))
2641 TEST_NEON(uqsub_4, uqsub(v0.V2S(), v1.V2S(), v2.V2S()))
2642 TEST_NEON(uqsub_5, uqsub(v0.V4S(), v1.V4S(), v2.V4S()))
2643 TEST_NEON(uqsub_6, uqsub(v0.V2D(), v1.V2D(), v2.V2D()))
2644 TEST_NEON(uqsub_7, uqsub(b0, b1, b2))
2645 TEST_NEON(uqsub_8, uqsub(h0, h1, h2))
2646 TEST_NEON(uqsub_9, uqsub(s0, s1, s2))
[all …]
Dtest-disasm-sve-aarch64.cc2212 COMPARE(uqsub(z9.VnB(), z13.VnB(), z13.VnB()), "uqsub z9.b, z13.b, z13.b"); in TEST()
2213 COMPARE(uqsub(z11.VnH(), z15.VnH(), z11.VnH()), "uqsub z11.h, z15.h, z11.h"); in TEST()
2214 COMPARE(uqsub(z13.VnS(), z17.VnS(), z13.VnS()), "uqsub z13.s, z17.s, z13.s"); in TEST()
2215 COMPARE(uqsub(z15.VnD(), z19.VnD(), z15.VnD()), "uqsub z15.d, z19.d, z15.d"); in TEST()
3133 COMPARE(uqsub(z10.VnB(), z10.VnB(), 27), "uqsub z10.b, z10.b, #27"); in TEST()
3134 COMPARE(uqsub(z11.VnH(), z11.VnH(), 117), "uqsub z11.h, z11.h, #117"); in TEST()
3135 COMPARE(uqsub(z12.VnS(), z12.VnS(), 138 * 256), in TEST()
3137 COMPARE(uqsub(z13.VnD(), z13.VnD(), 245 * 256), in TEST()
6772 COMPARE(uqsub(z10.VnB(), p3.Merging(), z10.VnB(), z1.VnB()), in TEST()
6774 COMPARE(uqsub(z10.VnD(), p3.Merging(), z10.VnD(), z1.VnD()), in TEST()
[all …]
Dtest-api-movprfx-aarch64.cc1254 __ uqsub(z9.VnD(), z9.VnD(), 42); in TEST() local
1678 __ uqsub(z13.VnH(), z13.VnH(), 42); in TEST() local
2364 __ uqsub(z20.VnB(), p0.Merging(), z20.VnB(), z6.VnB()); in TEST() local
3539 __ uqsub(z20.VnB(), p0.Merging(), z20.VnB(), z20.VnB()); in TEST() local
3682 __ uqsub(z20.VnB(), p0.Merging(), z20.VnB(), z6.VnB()); in TEST() local
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour2020 0x~~~~~~~~~~~~~~~~ 7e3a2e9c uqsub b28, b20, b26
2021 0x~~~~~~~~~~~~~~~~ 7eea2ce0 uqsub d0, d7, d10
2022 0x~~~~~~~~~~~~~~~~ 7e672f1a uqsub h26, h24, h7
2023 0x~~~~~~~~~~~~~~~~ 7eb02ef7 uqsub s23, s23, s16
2024 0x~~~~~~~~~~~~~~~~ 6e382e0e uqsub v14.16b, v16.16b, v24.16b
2025 0x~~~~~~~~~~~~~~~~ 6ee62e2b uqsub v11.2d, v17.2d, v6.2d
2026 0x~~~~~~~~~~~~~~~~ 2ea82d4a uqsub v10.2s, v10.2s, v8.2s
2027 0x~~~~~~~~~~~~~~~~ 2e6c2de9 uqsub v9.4h, v15.4h, v12.4h
2028 0x~~~~~~~~~~~~~~~~ 6ea72e57 uqsub v23.4s, v18.4s, v7.4s
2029 0x~~~~~~~~~~~~~~~~ 2e312e69 uqsub v9.8b, v19.8b, v17.8b
[all …]
Dlog-disasm2020 0x~~~~~~~~~~~~~~~~ 7e3a2e9c uqsub b28, b20, b26
2021 0x~~~~~~~~~~~~~~~~ 7eea2ce0 uqsub d0, d7, d10
2022 0x~~~~~~~~~~~~~~~~ 7e672f1a uqsub h26, h24, h7
2023 0x~~~~~~~~~~~~~~~~ 7eb02ef7 uqsub s23, s23, s16
2024 0x~~~~~~~~~~~~~~~~ 6e382e0e uqsub v14.16b, v16.16b, v24.16b
2025 0x~~~~~~~~~~~~~~~~ 6ee62e2b uqsub v11.2d, v17.2d, v6.2d
2026 0x~~~~~~~~~~~~~~~~ 2ea82d4a uqsub v10.2s, v10.2s, v8.2s
2027 0x~~~~~~~~~~~~~~~~ 2e6c2de9 uqsub v9.4h, v15.4h, v12.4h
2028 0x~~~~~~~~~~~~~~~~ 6ea72e57 uqsub v23.4s, v18.4s, v7.4s
2029 0x~~~~~~~~~~~~~~~~ 2e312e69 uqsub v9.8b, v19.8b, v17.8b
[all …]
Dlog-cpufeatures-custom2019 0x~~~~~~~~~~~~~~~~ 7e3a2e9c uqsub b28, b20, b26 ### {NEON} ###
2020 0x~~~~~~~~~~~~~~~~ 7eea2ce0 uqsub d0, d7, d10 ### {NEON} ###
2021 0x~~~~~~~~~~~~~~~~ 7e672f1a uqsub h26, h24, h7 ### {NEON} ###
2022 0x~~~~~~~~~~~~~~~~ 7eb02ef7 uqsub s23, s23, s16 ### {NEON} ###
2023 0x~~~~~~~~~~~~~~~~ 6e382e0e uqsub v14.16b, v16.16b, v24.16b ### {NEON} ###
2024 0x~~~~~~~~~~~~~~~~ 6ee62e2b uqsub v11.2d, v17.2d, v6.2d ### {NEON} ###
2025 0x~~~~~~~~~~~~~~~~ 2ea82d4a uqsub v10.2s, v10.2s, v8.2s ### {NEON} ###
2026 0x~~~~~~~~~~~~~~~~ 2e6c2de9 uqsub v9.4h, v15.4h, v12.4h ### {NEON} ###
2027 0x~~~~~~~~~~~~~~~~ 6ea72e57 uqsub v23.4s, v18.4s, v7.4s ### {NEON} ###
2028 0x~~~~~~~~~~~~~~~~ 2e312e69 uqsub v9.8b, v19.8b, v17.8b ### {NEON} ###
[all …]
Dlog-cpufeatures2019 0x~~~~~~~~~~~~~~~~ 7e3a2e9c uqsub b28, b20, b26 // Needs: NEON
2020 0x~~~~~~~~~~~~~~~~ 7eea2ce0 uqsub d0, d7, d10 // Needs: NEON
2021 0x~~~~~~~~~~~~~~~~ 7e672f1a uqsub h26, h24, h7 // Needs: NEON
2022 0x~~~~~~~~~~~~~~~~ 7eb02ef7 uqsub s23, s23, s16 // Needs: NEON
2023 0x~~~~~~~~~~~~~~~~ 6e382e0e uqsub v14.16b, v16.16b, v24.16b // Needs: NEON
2024 0x~~~~~~~~~~~~~~~~ 6ee62e2b uqsub v11.2d, v17.2d, v6.2d // Needs: NEON
2025 0x~~~~~~~~~~~~~~~~ 2ea82d4a uqsub v10.2s, v10.2s, v8.2s // Needs: NEON
2026 0x~~~~~~~~~~~~~~~~ 2e6c2de9 uqsub v9.4h, v15.4h, v12.4h // Needs: NEON
2027 0x~~~~~~~~~~~~~~~~ 6ea72e57 uqsub v23.4s, v18.4s, v7.4s // Needs: NEON
2028 0x~~~~~~~~~~~~~~~~ 2e312e69 uqsub v9.8b, v19.8b, v17.8b // Needs: NEON
[all …]
Dlog-cpufeatures-colour2019 0x~~~~~~~~~~~~~~~~ 7e3a2e9c uqsub b28, b20, b26 NEON
2020 0x~~~~~~~~~~~~~~~~ 7eea2ce0 uqsub d0, d7, d10 NEON
2021 0x~~~~~~~~~~~~~~~~ 7e672f1a uqsub h26, h24, h7 NEON
2022 0x~~~~~~~~~~~~~~~~ 7eb02ef7 uqsub s23, s23, s16 NEON
2023 0x~~~~~~~~~~~~~~~~ 6e382e0e uqsub v14.16b, v16.16b, v24.16b NEON
2024 0x~~~~~~~~~~~~~~~~ 6ee62e2b uqsub v11.2d, v17.2d, v6.2d NEON
2025 0x~~~~~~~~~~~~~~~~ 2ea82d4a uqsub v10.2s, v10.2s, v8.2s NEON
2026 0x~~~~~~~~~~~~~~~~ 2e6c2de9 uqsub v9.4h, v15.4h, v12.4h NEON
2027 0x~~~~~~~~~~~~~~~~ 6ea72e57 uqsub v23.4s, v18.4s, v7.4s NEON
2028 0x~~~~~~~~~~~~~~~~ 2e312e69 uqsub v9.8b, v19.8b, v17.8b NEON
[all …]
/external/capstone/arch/AArch64/
DAArch64MappingInsnOp.inc8745 { /* AArch64_UQSUBv16i8, ARM64_INS_UQSUB: uqsub.16b $rd, $rn, $rm| */
8749 { /* AArch64_UQSUBv1i16, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */
8753 { /* AArch64_UQSUBv1i32, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */
8757 { /* AArch64_UQSUBv1i64, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */
8761 { /* AArch64_UQSUBv1i8, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */
8765 { /* AArch64_UQSUBv2i32, ARM64_INS_UQSUB: uqsub.2s $rd, $rn, $rm| */
8769 { /* AArch64_UQSUBv2i64, ARM64_INS_UQSUB: uqsub.2d $rd, $rn, $rm| */
8773 { /* AArch64_UQSUBv4i16, ARM64_INS_UQSUB: uqsub.4h $rd, $rn, $rm| */
8777 { /* AArch64_UQSUBv4i32, ARM64_INS_UQSUB: uqsub.4s $rd, $rn, $rm| */
8781 { /* AArch64_UQSUBv8i16, ARM64_INS_UQSUB: uqsub.8h $rd, $rn, $rm| */
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12610 "uqshrn\007uqshrn2\007uqshrnb\007uqshrnt\005uqsub\006uqsubr\005uqxtn\006"
19746 …{ 6687 /* uqsub */, AArch64::UQSUBv1i16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasNEON, { MCK_FPR…
19747 …{ 6687 /* uqsub */, AArch64::UQSUBv1i32, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasNEON, { MCK_FPR…
19748 …{ 6687 /* uqsub */, AArch64::UQSUBv1i64, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasNEON, { MCK_FPR…
19749 …{ 6687 /* uqsub */, AArch64::UQSUBv1i8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasNEON, { MCK_FPR8…
19750 …{ 6687 /* uqsub */, AArch64::UQSUB_ZI_H, Convert__SVEVectorHReg1_0__Tie0_1_2__SVEAddSubImm162_2, A…
19751 …{ 6687 /* uqsub */, AArch64::UQSUB_ZZZ_H, Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHR…
19752 …{ 6687 /* uqsub */, AArch64::UQSUB_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, A…
19753 …{ 6687 /* uqsub */, AArch64::UQSUB_ZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSR…
19754 …{ 6687 /* uqsub */, AArch64::UQSUB_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2, A…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td92 defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub", usubsat>;
114 defm UQSUB_ZI : sve_int_arith_imm0<0b111, "uqsub", usubsat>;
1358 defm UQSUB_ZPmZ : sve2_int_arith_pred<0b110110, "uqsub">;
/external/vixl/src/aarch64/
Dassembler-aarch64.h2504 void uqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm);
5802 void uqsub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
5805 void uqsub(const ZRegister& zd,
6764 void uqsub(const ZRegister& zd,

12