D | logic-aarch64.cc | 1544 LogicVRegister extendedreg = uxtl(vform, temp2, src); in ushll() 3101 LogicVRegister Simulator::uxtl(VectorFormat vform, in uxtl() function in vixl::aarch64::Simulator 3136 return uxtl(vform, dst, src, /* is_2 = */ true); in uxtl2() 3467 uxtl(vform, temp1, src1); in uaddl() 3468 uxtl(vform, temp2, src2); in uaddl() 3491 uxtl(vform, temp, src2); in uaddw() 3559 uxtl(vform, temp1, src1); in usubl() 3560 uxtl(vform, temp2, src2); in usubl() 3583 uxtl(vform, temp, src2); in usubw() 3651 uxtl(vform, temp1, src1); in uabal() [all …]
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