Searched refs:v_cndmask_b32_e64 (Results 1 – 25 of 30) sorted by relevance
12
34 ; SI: v_cndmask_b32_e6438 ; SI: v_cndmask_b32_e6442 ; SI-DAG: v_cndmask_b32_e6443 ; SI-DAG: v_cndmask_b32_e6447 ; SI-DAG: v_cndmask_b32_e6448 ; SI-DAG: v_cndmask_b32_e6451 ; SI-DAG: v_cndmask_b32_e6452 ; SI-DAG: v_cndmask_b32_e64118 ; SI-DAG: v_cndmask_b32_e64122 ; SI-DAG: v_cndmask_b32_e64[all …]
8 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc25 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc42 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc56 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc70 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc84 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc98 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc112 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc155 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc168 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc[all …]
18 ; SI: v_cndmask_b32_e6419 ; SI: v_cndmask_b32_e6433 ; SI: v_cndmask_b32_e6434 ; SI: v_cndmask_b32_e6449 ; SI: v_cndmask_b32_e6450 ; SI: v_cndmask_b32_e64
101 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc133 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc146 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc160 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc174 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc188 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc339 ; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,341 ; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,343 ; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,360 ; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,[all …]
14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc29 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]45 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]61 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]76 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]89 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]104 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc118 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc132 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc150 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc[all …]
17 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]18 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]44 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]45 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]72 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]73 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
62 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc83 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc95 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc106 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc117 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc128 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
8 ; SI: v_cndmask_b32_e6424 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]]121 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]]136 ; XSI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CMP0]]160 ; SI-NEXT: v_cndmask_b32_e64
7 ; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}}27 ; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}}
68 ; SI: v_cndmask_b32_e64 [[V_CMP:v[0-9]+]], 0, -1, [[CMP_IF]]73 ; SI: v_cndmask_b32_e64 [[V_CMP]], 0, -1, [[CMP_ELSE]]76 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP_CMP]]
10 ; GCN: v_cndmask_b32_e64 v1, 0, 1, s{{\[[0-9]+:[0-9]+\]}}37 ; GCN: v_cndmask_b32_e64 v1, 0, 1, s{{\[[0-9]+:[0-9]+\]}}
13 ; We can't fold the SGPRs into v_cndmask_b32_e64, because it already30 ; SI: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, -1
81 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]92 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0105 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0
81 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]92 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1.0105 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1.0
4 ; CHECK: v_cndmask_b32_e64 v0, 0, 1, exec20 ; CHECK-DAG: v_cndmask_b32_e64 [[VAR:v[0-9]+]], 0, 1, [[LIVE]]
24 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], [[VCTLZ]], 32, [[CMPZ]]40 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], [[CTLZ]], 32, vcc103 ; SI-DAG: v_cndmask_b32_e64 [[CORRECTED_FFBH:v[0-9]+]], [[FFBH]], 32, vcc145 ; SI-DAG: v_cndmask_b32_e64 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[ADD]], [[CMPHI]]148 ; SI-DAG: v_cndmask_b32_e64 v[[CLTZ_LO:[0-9]+]], v[[CTLZ:[0-9]+]], 64, vcc
5 ; CHECK: v_cndmask_b32_e64
6 ; CHECK-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, 1.0, [[CMP]]
10 ; SI: v_cndmask_b32_e6428 ;SI: v_cndmask_b32_e64
77 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]89 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
23 ; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]]
5 ; GCN: v_cndmask_b32_e6427 ; GCN: v_cndmask_b32_e64 v[[LOREG:[0-9]+]], 0, -1, vcc
72 ; SI-NEXT: v_cndmask_b32_e64
205 v_cndmask_b32_e64 v1, v3, v5, s[4:5] label209 v_cndmask_b32_e64 v1, v3, v5, vcc label