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Searched refs:v_lshlrev_b32 (Results 1 – 11 of 11) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeonsi/glsl_tests/
Dbitfield_insert.glsl10 ; GCN-NEXT: v_lshlrev_b32
30 ; GCN-NEXT: v_lshlrev_b32
Dpack_unpack_half.glsl10 ; GCN-NEXT: v_lshlrev_b32
/external/llvm/test/MC/AMDGPU/
Dvop2.s223 v_lshlrev_b32 v1, v2, v3 label
Dvop_dpp.s410 v_lshlrev_b32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
Dvop_sdwa.s417 v_lshlrev_b32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
/external/llvm/test/CodeGen/AMDGPU/
Dcvt_f32_ubyte.ll68 ; SI-DAG: v_lshlrev_b32
/external/mesa3d/src/amd/compiler/
Daco_lower_to_hw_instr.cpp1109 …bld.vop2(aco_opcode::v_lshlrev_b32, lo_half, Operand(32 - bits), Operand(lo_reg, lo_half.regClass(… in do_copy()
1254 bld.vop2(aco_opcode::v_lshlrev_b32, def_hi, Operand(16u), hi); in do_pack_2x16()
1278 bld.vop2(aco_opcode::v_lshlrev_b32, def_hi, Operand(16u), hi); in do_pack_2x16()
1308 bld.vop2(aco_opcode::v_lshlrev_b32, def_hi, Operand(16u), lo); in do_pack_2x16()
Daco_optimizer.cpp1454 case aco_opcode::v_lshlrev_b32: in label_instruction()
2857 …else combine_three_valu_op(ctx, instr, aco_opcode::v_lshlrev_b32, aco_opcode::v_lshl_or_b32, "210"… in combine_instruction()
2870 …else combine_three_valu_op(ctx, instr, aco_opcode::v_lshlrev_b32, aco_opcode::v_lshl_add_u32, "210… in combine_instruction()
2883 } else if (instr->opcode == aco_opcode::v_lshlrev_b32 && ctx.program->chip_class >= GFX9) { in combine_instruction()
Daco_instruction_selection.cpp207 Operand index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index); in emit_bpermute()
217 Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index); in emit_bpermute()
1442 emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true); in visit_alu_instr()
2390 mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa); in visit_alu_instr()
4632 …alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == AC_FETCH_FORMAT_SNO… in adjust_vertex_fetch_alpha()
5660 sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index); in adjust_sample_index_using_fmask()
6915 Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, in visit_load_sample_mask_in()
7606 addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr); in visit_intrinsic()
7616 addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr); in visit_intrinsic()
7632 addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr); in visit_intrinsic()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOP2Instructions.td482 defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, lshl_rev, "v_lshl_b32">;
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td1542 vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag,