Searched refs:v_max_i32 (Results 1 – 11 of 11) sorted by relevance
| /external/mesa3d/src/gallium/drivers/radeonsi/glsl_tests/ |
| D | minmax.i32.glsl | 23 ; GCN-NEXT: v_max_i32
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| /external/llvm/test/MC/AMDGPU/ |
| D | vop2.s | 188 v_max_i32 v1, v2, v3 label
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| D | vop_dpp.s | 390 v_max_i32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
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| D | vop_sdwa.s | 397 v_max_i32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_lower_to_hw_instr.cpp | 106 return aco_opcode::v_max_i32; in get_reduce_opcode()
110 return aco_opcode::v_max_i32; in get_reduce_opcode()
149 case imax32: return aco_opcode::v_max_i32; in get_reduce_opcode()
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| D | aco_optimizer.cpp | 554 case aco_opcode::v_max_i32: in can_swap_operands()
1466 case aco_opcode::v_max_i32: in label_instruction()
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| D | aco_instruction_selection.cpp | 1277 … bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src)); in visit_alu_instr()
1317 emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true); in visit_alu_instr()
2464 exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent); in visit_alu_instr()
10495 values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), in export_fs_mrt_color()
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | smed3.ll | 25 ; GCN: v_max_i32
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| D | sext-in-reg.ll | 423 ; SI: v_max_i32
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | VOP2Instructions.td | 477 defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 1527 defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32>;
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