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Searched refs:v_or_b32 (Results 1 – 14 of 14) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dunaligned-load-store.ll104 ; SI-NOT: v_or_b32
107 ; SI-NOT: v_or_b32
111 ; SI-NOT: v_or_b32
115 ; SI-NOT: v_or_b32
119 ; SI-NOT: v_or_b32
123 ; SI-NOT: v_or_b32
127 ; SI-NOT: v_or_b32
131 ; SI-NOT: v_or_b32
151 ; SI-NOT: v_or_b32
154 ; SI-NOT: v_or_b32
[all …]
Drotl.i64.ll26 ; BOTH: v_or_b32
27 ; BOTH: v_or_b32
Drotr.i64.ll25 ; BOTH: v_or_b32
26 ; BOTH: v_or_b32
Dcopy-illegal-type.ll60 ; SI: v_or_b32
78 ; SI-DAG: v_or_b32
Dcvt_f32_ubyte.ll69 ; SI-DAG: v_or_b32
Dindirect-addressing-si.ll22 ; XXX: Could do v_or_b32 directly
/external/llvm/test/MC/AMDGPU/
Dvop2.s231 v_or_b32 v1, v2, v3 label
Dvop_dpp.s414 v_or_b32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
Dvop_sdwa.s421 v_or_b32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
/external/mesa3d/src/amd/compiler/
Daco_lower_to_hw_instr.cpp163 case ior32: return aco_opcode::v_or_b32; in get_reduce_opcode()
231 bld.vop2_dpp(aco_opcode::v_or_b32, dst[0], src0[0], src1[0], in emit_int64_dpp_op()
233 bld.vop2_dpp(aco_opcode::v_or_b32, dst[1], src0[1], src1[1], in emit_int64_dpp_op()
344 bld.vop2(aco_opcode::v_or_b32, dst[0], src0[0], src1[0]); in emit_int64_op()
345 bld.vop2(aco_opcode::v_or_b32, dst[1], src0[1], src1[1]); in emit_int64_op()
1045 bld.vop2(aco_opcode::v_or_b32, dst, Operand(op.constantValue() << offset), def_op); in copy_constant()
1257 bld.vop2(aco_opcode::v_or_b32, def, Operand(lo.constantValue()), Operand(def.physReg(), v1)); in do_pack_2x16()
1266 …bld.vop2(aco_opcode::v_or_b32, def, Operand(hi.constantValue() << 16u), Operand(def.physReg(), v1)… in do_pack_2x16()
Daco_optimizer.cpp547 case aco_opcode::v_or_b32: in can_swap_operands()
1322 instr->opcode = aco_opcode::v_or_b32; in label_instruction()
1453 case aco_opcode::v_or_b32: in label_instruction()
2851 } else if (instr->opcode == aco_opcode::v_or_b32 && ctx.program->chip_class >= GFX9) { in combine_instruction()
2853 …else if (combine_three_valu_op(ctx, instr, aco_opcode::v_or_b32, aco_opcode::v_or3_b32, "012", 1 |… in combine_instruction()
Daco_instruction_selection.cpp1371 emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true); in visit_alu_instr()
1373 emit_vop2_instruction_logic64(ctx, instr, aco_opcode::v_or_b32, dst); in visit_alu_instr()
2389 mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa); in visit_alu_instr()
2466 mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa); in visit_alu_instr()
7869 … bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id); in visit_intrinsic()
8802 pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc); in visit_tex()
8807 pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack); in visit_tex()
10193 out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]); in export_vs_psiz_layer_viewport()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOP2Instructions.td484 defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>;
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td1547 defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>;