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Searched refs:v_sub_f32 (Results 1 – 8 of 8) sorted by relevance

/external/llvm/test/MC/AMDGPU/
Dvop3.s219 v_sub_f32 v1, v3, s5 label
Dvop2.s129 v_sub_f32 v1, v2, v3 label
Dvop_dpp.s358 v_sub_f32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
Dvop_sdwa.s365 v_sub_f32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
/external/mesa3d/src/amd/compiler/
Daco_optimizer.cpp570 case aco_opcode::v_sub_f32: in can_swap_operands()
923 instr->opcode = i ? aco_opcode::v_sub_f32 : aco_opcode::v_subrev_f32; in label_instruction()
2711 instr->opcode == aco_opcode::v_sub_f32 || in combine_instruction()
2804 if (instr->opcode == aco_opcode::v_sub_f32 || instr->opcode == aco_opcode::v_sub_f16) in combine_instruction()
Daco_instruction_selection.cpp1810 emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false); in visit_alu_instr()
2949 tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2); in visit_alu_instr()
2953 tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl); in visit_alu_instr()
5056 tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0x3f800000u /* 1.0f */), tmp); in visit_load_tess_coord()
7495 ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1); in emit_interp_center()
7496 ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2); in emit_interp_center()
7498 ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1); in emit_interp_center()
7499 ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2); in emit_interp_center()
7503 ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1); in emit_interp_center()
7505 ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1); in emit_interp_center()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOP2Instructions.td466 defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, fsub>;
467 defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td1490 defm V_SUB_F32 : VOP2Inst <vop2<0x4, 0x2>, "v_sub_f32", VOP_F32_F32_F32, fsub>;
1492 VOP_F32_F32_F32, null_frag, "v_sub_f32"