| /external/llvm/test/MC/ARM/ |
| D | thumb-neon-v8.s | 30 vcvtn.s32.f32 d15, d17
31 @ CHECK: vcvtn.s32.f32 d15, d17 @ encoding: [0xbb,0xff,0x21,0xf1]
32 vcvtn.u32.f32 d5, d3
33 @ CHECK: vcvtn.u32.f32 d5, d3 @ encoding: [0xbb,0xff,0x83,0x51]
34 vcvtn.s32.f32 q3, q8
35 @ CHECK: vcvtn.s32.f32 q3, q8 @ encoding: [0xbb,0xff,0x60,0x61]
36 vcvtn.u32.f32 q5, q3
37 @ CHECK: vcvtn.u32.f32 q5, q3 @ encoding: [0xbb,0xff,0xc6,0xa1]
|
| D | neon-v8.s | 30 vcvtn.s32.f32 d15, d17
31 @ CHECK: vcvtn.s32.f32 d15, d17 @ encoding: [0x21,0xf1,0xbb,0xf3]
32 vcvtn.u32.f32 d5, d3
33 @ CHECK: vcvtn.u32.f32 d5, d3 @ encoding: [0x83,0x51,0xbb,0xf3]
34 vcvtn.s32.f32 q3, q8
35 @ CHECK: vcvtn.s32.f32 q3, q8 @ encoding: [0x60,0x61,0xbb,0xf3]
36 vcvtn.u32.f32 q5, q3
37 @ CHECK: vcvtn.u32.f32 q5, q3 @ encoding: [0xc6,0xa1,0xbb,0xf3]
|
| D | thumb-fp-armv8.s | 35 vcvtn.s32.f32 s6, s23
36 @ CHECK: vcvtn.s32.f32 s6, s23 @ encoding: [0xbd,0xfe,0xeb,0x3a]
37 vcvtn.s32.f64 s6, d23
38 @ CHECK: vcvtn.s32.f64 s6, d23 @ encoding: [0xbd,0xfe,0xe7,0x3b]
52 vcvtn.u32.f32 s6, s23
53 @ CHECK: vcvtn.u32.f32 s6, s23 @ encoding: [0xbd,0xfe,0x6b,0x3a]
54 vcvtn.u32.f64 s6, d23
55 @ CHECK: vcvtn.u32.f64 s6, d23 @ encoding: [0xbd,0xfe,0x67,0x3b]
|
| D | fp-armv8.s | 32 vcvtn.s32.f32 s6, s23
33 @ CHECK: vcvtn.s32.f32 s6, s23 @ encoding: [0xeb,0x3a,0xbd,0xfe]
34 vcvtn.s32.f64 s6, d23
35 @ CHECK: vcvtn.s32.f64 s6, d23 @ encoding: [0xe7,0x3b,0xbd,0xfe]
49 vcvtn.u32.f32 s6, s23
50 @ CHECK: vcvtn.u32.f32 s6, s23 @ encoding: [0x6b,0x3a,0xbd,0xfe]
51 vcvtn.u32.f64 s6, d23
52 @ CHECK: vcvtn.u32.f64 s6, d23 @ encoding: [0x67,0x3b,0xbd,0xfe]
|
| D | directive-arch_extension-simd.s | 37 vcvtn.s32.f32 s0, s0
39 vcvtn.u32.f32 s0, s0
41 vcvtn.s32.f64 s0, d0
43 vcvtn.u32.f64 s0, d0
145 vcvtn.s32.f32 s0, s0
147 vcvtn.u32.f32 s0, s0
149 vcvtn.s32.f64 s0, d0
151 vcvtn.u32.f64 s0, d0
|
| D | fullfp16-neon.s | 312 vcvtn.s16.f16 d0, d1
313 vcvtn.s16.f16 q0, q1
314 vcvtn.u16.f16 d0, d1
315 vcvtn.u16.f16 q0, q1
316 @ ARM: vcvtn.s16.f16 d0, d1 @ encoding: [0x01,0x01,0xb7,0xf3]
317 @ ARM: vcvtn.s16.f16 q0, q1 @ encoding: [0x42,0x01,0xb7,0xf3]
318 @ ARM: vcvtn.u16.f16 d0, d1 @ encoding: [0x81,0x01,0xb7,0xf3]
319 @ ARM: vcvtn.u16.f16 q0, q1 @ encoding: [0xc2,0x01,0xb7,0xf3]
320 @ THUMB: vcvtn.s16.f16 d0, d1 @ encoding: [0xb7,0xff,0x01,0x01]
321 @ THUMB: vcvtn.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x01]
[all …]
|
| D | directive-arch_extension-fp.s | 65 vcvtn.s32.f32 s0, s0
67 vcvtn.u32.f32 s0, s0
69 vcvtn.s32.f64 s0, d0
71 vcvtn.u32.f64 s0, d0
201 vcvtn.s32.f32 s0, s0
203 vcvtn.u32.f32 s0, s0
205 vcvtn.s32.f64 s0, d0
207 vcvtn.u32.f64 s0, d0
|
| D | fullfp16.s | 117 vcvtn.s32.f16 s6, s23
118 @ ARM: vcvtn.s32.f16 s6, s23 @ encoding: [0xeb,0x39,0xbd,0xfe]
119 @ THUMB: vcvtn.s32.f16 s6, s23 @ encoding: [0xbd,0xfe,0xeb,0x39]
133 vcvtn.u32.f16 s6, s23
134 @ ARM: vcvtn.u32.f16 s6, s23 @ encoding: [0x6b,0x39,0xbd,0xfe]
135 @ THUMB: vcvtn.u32.f16 s6, s23 @ encoding: [0xbd,0xfe,0x6b,0x39]
|
| D | fullfp16-neon-neg.s | 225 vcvtn.s16.f16 d0, d1
226 vcvtn.s16.f16 q0, q1
227 vcvtn.u16.f16 d0, d1
228 vcvtn.u16.f16 q0, q1
|
| D | fullfp16-neg.s | 86 vcvtn.s32.f16 s6, s23
98 vcvtn.u32.f16 s6, s23
|
| D | invalid-fp-armv8.s | 61 vcvtn.u32.f64 d3, s2
|
| /external/capstone/suite/MC/ARM/ |
| D | neon-v8.s.cs | 14 0x21,0xf1,0xbb,0xf3 = vcvtn.s32.f32 d15, d17
15 0x83,0x51,0xbb,0xf3 = vcvtn.u32.f32 d5, d3
16 0x60,0x61,0xbb,0xf3 = vcvtn.s32.f32 q3, q8
17 0xc6,0xa1,0xbb,0xf3 = vcvtn.u32.f32 q5, q3
|
| D | thumb-neon-v8.s.cs | 14 0xbb,0xff,0x21,0xf1 = vcvtn.s32.f32 d15, d17
15 0xbb,0xff,0x83,0x51 = vcvtn.u32.f32 d5, d3
16 0xbb,0xff,0x60,0x61 = vcvtn.s32.f32 q3, q8
17 0xbb,0xff,0xc6,0xa1 = vcvtn.u32.f32 q5, q3
|
| D | thumb-fp-armv8.s.cs | 12 0xbd,0xfe,0xeb,0x3a = vcvtn.s32.f32 s6, s23
13 0xbd,0xfe,0xe7,0x3b = vcvtn.s32.f64 s6, d23
20 0xbd,0xfe,0x6b,0x3a = vcvtn.u32.f32 s6, s23
21 0xbd,0xfe,0x67,0x3b = vcvtn.u32.f64 s6, d23
|
| D | fp-armv8.s.cs | 12 0xeb,0x3a,0xbd,0xfe = vcvtn.s32.f32 s6, s23
13 0xe7,0x3b,0xbd,0xfe = vcvtn.s32.f64 s6, d23
20 0x6b,0x3a,0xbd,0xfe = vcvtn.u32.f32 s6, s23
21 0x67,0x3b,0xbd,0xfe = vcvtn.u32.f64 s6, d23
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neon-v8.txt | 31 # CHECK: vcvtn.s32.f32 d15, d17
33 # CHECK: vcvtn.u32.f32 d5, d3
35 # CHECK: vcvtn.s32.f32 q3, q8
37 # CHECK: vcvtn.u32.f32 q5, q3
|
| D | thumb-neon-v8.txt | 31 # CHECK: vcvtn.s32.f32 d15, d17
33 # CHECK: vcvtn.u32.f32 d5, d3
35 # CHECK: vcvtn.s32.f32 q3, q8
37 # CHECK: vcvtn.u32.f32 q5, q3
|
| D | thumb-fp-armv8.txt | 39 # CHECK: vcvtn.s32.f32 s6, s23
42 # CHECK: vcvtn.s32.f64 s6, d23
63 # CHECK: vcvtn.u32.f32 s6, s23
66 # CHECK: vcvtn.u32.f64 s6, d23
|
| D | fp-armv8.txt | 35 # CHECK: vcvtn.s32.f32 s6, s23
38 # CHECK: vcvtn.s32.f64 s6, d23
59 # CHECK: vcvtn.u32.f32 s6, s23
62 # CHECK: vcvtn.u32.f64 s6, d23
|
| D | fullfp16-neon-thumb.txt | 203 # CHECK: vcvtn.s16.f16 d0, d1
204 # CHECK: vcvtn.s16.f16 q0, q1
205 # CHECK: vcvtn.u16.f16 d0, d1
206 # CHECK: vcvtn.u16.f16 q0, q1
|
| D | fullfp16-neon-arm.txt | 203 # CHECK: vcvtn.s16.f16 d0, d1
204 # CHECK: vcvtn.s16.f16 q0, q1
205 # CHECK: vcvtn.u16.f16 d0, d1
206 # CHECK: vcvtn.u16.f16 q0, q1
|
| D | fullfp16-arm.txt | 85 # CHECK: vcvtn.s32.f16 s6, s23
97 # CHECK: vcvtn.u32.f16 s6, s23
|
| D | fullfp16-thumb.txt | 85 # CHECK: vcvtn.s32.f16 s6, s23
97 # CHECK: vcvtn.u32.f16 s6, s23
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vcvt-v8.ll | 20 ; CHECK: vcvtn.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
28 ; CHECK: vcvtn.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
84 ; CHECK: vcvtn.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
92 ; CHECK: vcvtn.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
|
| /external/vixl/src/aarch32/ |
| D | disasm-aarch32.h | 1739 void vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
1741 void vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
1743 void vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
1745 void vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
|