| /external/llvm/test/MC/ARM/ |
| D | vfp4.s | 64 @ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee]
65 @ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b]
67 @ THUMB_V7EM-ERRORS-NEXT: vfnms.f64 d16, d18, d17
68 vfnms.f64 d16, d18, d17
70 @ ARM: vfnms.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0x92,0xee]
71 @ THUMB: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a]
72 @ THUMB_V7EM: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a]
73 vfnms.f32 s2, s4, s0
|
| D | fullfp16.s | 209 vfnms.f16 s2, s7, s4
210 @ ARM: vfnms.f16 s2, s7, s4 @ encoding: [0x82,0x19,0x93,0xee]
211 @ THUMB: vfnms.f16 s2, s7, s4 @ encoding: [0x93,0xee,0x82,0x19]
|
| D | single-precision-fp.s | 28 vfnms.f64 d10, d11, d12
44 @ CHECK-ERRORS-NEXT: vfnms.f64 d10, d11, d12
|
| D | fullfp16-neg.s | 155 vfnms.f16 s2, s7, s4
|
| /external/capstone/suite/MC/ARM/ |
| D | vfp4-thumb.s.cs | 12 0xd2,0xee,0xa1,0x0b = vfnms.f64 d16, d18, d17
13 0x92,0xee,0x00,0x1a = vfnms.f32 s2, s4, s0
|
| D | vfp4.s.cs | 12 0xa1,0x0b,0xd2,0xee = vfnms.f64 d16, d18, d17
13 0x00,0x1a,0x92,0xee = vfnms.f32 s2, s4, s0
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | vfp4.txt | 15 # CHECK: vfnms.f64 d16, d18, d17
18 # CHECK: vfnms.f32 s2, s4, s0
|
| D | fullfp16-arm.txt | 154 # CHECK: vfnms.f16 s2, s7, s4
|
| D | fullfp16-thumb.txt | 154 # CHECK: vfnms.f16 s2, s7, s4
|
| /external/llvm/test/CodeGen/ARM/ |
| D | fusedMAC.ll | 56 ;CHECK: vfnms.f64
64 ;CHECK: vfnms.f32
146 ; CHECK: vfnms.f32
156 ; CHECK: vfnms.f64
166 ; CHECK: vfnms.f64
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 1977 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1985 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1995 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm",
2009 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
2016 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
2023 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 2223 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
2232 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
2243 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm",
2258 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
2268 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
2278 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 4503 void vfnms(
4505 void vfnms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vfnms() function
4506 vfnms(al, dt, rd, rn, rm); in vfnms()
4509 void vfnms(
4511 void vfnms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vfnms() function
4512 vfnms(al, dt, rd, rn, rm); in vfnms()
|
| D | disasm-aarch32.h | 1828 void vfnms(
1831 void vfnms(
|
| D | disasm-aarch32.cc | 4841 void Disassembler::vfnms( in vfnms() function in vixl::aarch32::Disassembler
4848 void Disassembler::vfnms( in vfnms() function in vixl::aarch32::Disassembler
23526 vfnms(CurrentCond(), in DecodeT32()
23552 vfnms(CurrentCond(), in DecodeT32()
66131 vfnms(condition, in DecodeA32()
66167 vfnms(condition, in DecodeA32()
|
| D | assembler-aarch32.cc | 17835 void Assembler::vfnms( in vfnms() function in vixl::aarch32::Assembler
17855 Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm); in vfnms()
17858 void Assembler::vfnms( in vfnms() function in vixl::aarch32::Assembler
17878 Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm); in vfnms()
|
| D | macro-assembler-aarch32.h | 7001 vfnms(cond, dt, rd, rn, rm); in Vfnms()
7016 vfnms(cond, dt, rd, rn, rm); in Vfnms()
|
| /external/capstone/arch/SystemZ/ |
| D | SystemZGenInsnNameMaps.inc | 1929 { SYSZ_INS_VFNMS, "vfnms" },
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrVector.td | 1277 def VFNMS : TernaryVRReFloatGeneric<"vfnms", 0xE79E>;
|
| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 2086 { /* ARM_VFNMSD, ARM_INS_VFNMS: vfnms${p}.f64 $dd, $dn, $dm */
2089 { /* ARM_VFNMSS, ARM_INS_VFNMS: vfnms${p}.f32 $sd, $sn, $sm */
|
| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 2086 { /* ARM_VFNMSD, ARM_INS_VFNMS: vfnms${p}.f64 $dd, $dn, $dm */
2089 { /* ARM_VFNMSS, ARM_INS_VFNMS: vfnms${p}.f32 $sd, $sn, $sm */
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9926 "vfnms\005vhadd\006vhcadd\005vhsub\005vidup\004vins\006viwdup\005vjcvt\004"
12480 …{ 2299 /* vfnms */, ARM::VFNMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_Has…
12481 …{ 2299 /* vfnms */, ARM::VFNMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_Has…
12482 …{ 2299 /* vfnms */, ARM::VFNMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_Has…
|