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Searched refs:virgl (Results 1 – 25 of 71) sorted by relevance

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/external/virglrenderer/server/
Drender_virgl.c40 const struct render_virgl *virgl = render_virgl_lock_struct(); in render_virgl_lookup_context() local
44 list_for_each_entry (struct render_context, iter, &virgl->contexts, head) { in render_virgl_lookup_context()
51 assert(list_is_singular(&virgl->contexts)); in render_virgl_lookup_context()
52 ctx = list_first_entry(&virgl->contexts, struct render_context, head); in render_virgl_lookup_context()
91 struct render_virgl *virgl = render_virgl_lock_struct(); in render_virgl_add_context() local
92 list_addtail(&ctx->head, &virgl->contexts); in render_virgl_add_context()
107 struct render_virgl *virgl = render_virgl_lock_struct(); in render_virgl_fini() local
109 if (virgl->init_count) { in render_virgl_fini()
110 virgl->init_count--; in render_virgl_fini()
111 if (!virgl->init_count) { in render_virgl_fini()
[all …]
D.clang-format26 - Regex: '^"(virgl|vrend_|c11/|util/|os/|pipe/|venus-protocol/|server/)'
/external/mesa3d/docs/
Dfeatures.txt39 ….30 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr, virgl, zink
72 …l DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr, virgl, panfrost, zink
85 GL 3.2, GLSL 1.50 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr, virgl, z…
100 GL 3.3, GLSL 3.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, virgl, zink
114 GL 4.0, GLSL 4.00 --- all DONE: i965/gen7+, nvc0, r600, radeonsi, llvmpipe, virgl
143 GL 4.1, GLSL 4.10 --- all DONE: i965/gen7+, nvc0, r600, radeonsi, llvmpipe, virgl
153 GL 4.2, GLSL 4.20 -- all DONE: i965/gen7+, nvc0, r600, radeonsi, llvmpipe, virgl
169 GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0, r600, radeonsi, llvmpipe, virgl
199 GL_ARB_clear_texture DONE (i965, nv50, softpipe, swr, virgl)
200 GL_ARB_enhanced_layouts DONE (i965, nv50, softpipe, virgl)
[all …]
/external/virglrenderer/src/
Dvirgl_util.h92 C(virgl, "virglrenderer") \
97 #define TRACE_SCOPE(SCOPE) TRACE_EVENT(virgl, SCOPE)
101 #define TRACE_SCOPE_BEGIN(SCOPE) TRACE_EVENT_BEGIN(virgl, SCOPE)
102 #define TRACE_SCOPE_END(SCOPE) do { TRACE_EVENT_END(virgl); (void)SCOPE; } while (0)
Dmeson.build223 'virgl',
253 description: 'virgl GL renderer',
254 subdirs: 'virgl'
263 install_headers('virglrenderer.h', subdir : 'virgl')
/external/mesa3d/src/gallium/
DAndroid.mk47 SUBDIRS += winsys/virgl/common winsys/virgl/drm winsys/virgl/vtest drivers/virgl
Dmeson.build146 subdir('winsys/virgl/common')
147 subdir('winsys/virgl/drm')
148 subdir('winsys/virgl/vtest')
149 subdir('drivers/virgl')
/external/mesa3d/docs/relnotes/
D18.1.9.rst70 - virgl: don't send a shader create with no data. (v2)
88 - winsys/virgl: avoid unintended behavior
89 - virgl: adjust strides when mapping temp-resources
93 - winsys/virgl: correct resource and handle allocation (v2)
D19.0.7.rst35 - virgl on OpenGL 3.3 host regressed to OpenGL 2.1
70 - virgl: Add a caps feature check version
71 - virgl: Assume sRGB write control for older guest kernels or
D18.2.7.rst89 - virgl: quadruple command buffer size
90 - virgl: avoid large inline transfers
91 - virgl: don't mark buffers as unclean after a write
D18.2.1.rst85 - virgl: don't send a shader create with no data. (v2)
98 - winsys/virgl: avoid unintended behavior
99 - virgl: adjust strides when mapping temp-resources
108 - winsys/virgl: correct resource and handle allocation (v2)
D19.1.0.rst339 - virgl: Fake MSAA when max samples is 1
1055 - virgl: handle fence_server_sync in winsys
1056 - virgl: hide fence internals from the driver
1057 - virgl: introduce virgl_drm_fence
1058 - virgl: fix fence fd version check
1059 - virgl: clear vertex_array_dirty
1060 - virgl: skip empty cmdbufs
1150 - virgl: enable elapsed time queries
1151 - virgl: ARB_query_buffer_object support
1152 - docs: update qbo support for virgl
[all …]
D19.1.1.rst39 - virgl on OpenGL 3.3 host regressed to OpenGL 2.1
73 - virgl: Assume sRGB write control for older guest kernels or
D18.2.5.rst79 - virgl/vtest-winsys: Use virgl version of bind flags
/external/virglrenderer/
DREADME.rst8 This repository lives at https://gitlab.freedesktop.org/virgl/virglrenderer.
43 `GitLab <https://gitlab.freedesktop.org/virgl/virglrenderer/-/issues>`_.
/external/virglrenderer/perf-testing/Docker/
Drun.sh71 -Dgallium-drivers=swrast,virgl,radeonsi,iris \
88 -Dgallium-drivers=swrast,virgl,radeonsi,iris \
/external/mesa3d/.gitlab-ci/
Dbuild-virglrenderer.sh14 git clone https://gitlab.freedesktop.org/virgl/virglrenderer.git --single-branch --no-checkout /vir…
/external/virglrenderer/ci/
Drun_ci_locally.sh9 DOCKER_IMAGE=${DOCKER_IMAGE:-registry.freedesktop.org/virgl/virglrenderer/debian/bullseye:2021-04-1…
/external/virglrenderer/src/venus/
D.clang-format26 - Regex: '^"(virgl|vrend_|c11/|util/|os/|pipe/|venus-protocol/|server/)'
/external/virglrenderer/src/proxy/
D.clang-format26 - Regex: '^"(virgl|vrend_|c11/|util/|os/|pipe/|venus-protocol/|server/)'
/external/mesa3d/src/gallium/drivers/virgl/
Dvirgl_driinfo.h.in1 // DriConf options specific to virgl
/external/virglrenderer/docs/
Dpiglit-notes.txt1 Some notes on piglit failures running on virgl.
/external/virglrenderer/.gitlab-ci/expectations/host/
Ddeqp-virgl-gles.toml12 renderer_check = "virgl"
/external/mesa3d/src/egl/
DAndroid.mk92 ifeq ($(BOARD_GPU_DRIVERS),virgl)
/external/virglrenderer/perf-testing/
Drun-trace-in-container.sh58 --virgl|-v)

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