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Searched refs:vlr (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/test/CodeGen/SystemZ/
Dvec-move-01.ll8 ; CHECK: vlr %v24, %v26
16 ; CHECK: vlr %v24, %v26
24 ; CHECK: vlr %v24, %v26
32 ; CHECK: vlr %v24, %v26
40 ; CHECK: vlr %v24, %v26
48 ; CHECK: vlr %v24, %v26
56 ; CHECK: vlr %v24, %v26
64 ; CHECK: vlr %v24, %v26
72 ; CHECK: vlr %v24, %v26
80 ; CHECK: vlr %v24, %v26
[all …]
Dvec-move-07.ll44 ; CHECK: vlr %v24, %v0
53 ; CHECK: vlr %v24, %v0
Dvec-args-07.ll12 ; CHECK: vlr %v24, %v31
Dvec-sub-01.ll47 ; CHECK-DAG: vlr %v[[A1:[0-5]]], %v24
48 ; CHECK-DAG: vlr %v[[A2:[0-5]]], %v26
Dvec-move-05.ll156 ; CHECK: vlr %v0, %v24
209 ; CHECK: vlr %v0, %v24
/external/XNNPACK/src/f32-ibilinear-chw/gen/
Dsse-p4.c144 const __m128 vlr = _mm_add_ps(vtltr, _mm_mul_ps(vldrd, valphav)); in xnn_f32_ibilinear_chw_ukernel__sse_p4() local
147 const float l = _mm_cvtss_f32(vlr); in xnn_f32_ibilinear_chw_ukernel__sse_p4()
148 const float r = _mm_cvtss_f32(_mm_shuffle_ps(vlr, vlr, 1)); in xnn_f32_ibilinear_chw_ukernel__sse_p4()
Dwasmsimd-p4.c148 const v128_t vlr = wasm_f32x4_add(vtltr, wasm_f32x4_mul(vldrd, valphav)); in xnn_f32_ibilinear_chw_ukernel__wasmsimd_p4() local
151 const float l = wasm_f32x4_extract_lane(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__wasmsimd_p4()
152 const float r = wasm_f32x4_extract_lane(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__wasmsimd_p4()
Dneonfma-p4.c155 const float32x2_t vlr = vfma_f32(vtltr, vldrd, valphav); in xnn_f32_ibilinear_chw_ukernel__neonfma_p4() local
158 const float l = vget_lane_f32(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__neonfma_p4()
159 const float r = vget_lane_f32(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__neonfma_p4()
Dneon-p4.c155 const float32x2_t vlr = vmla_f32(vtltr, vldrd, valphav); in xnn_f32_ibilinear_chw_ukernel__neon_p4() local
158 const float l = vget_lane_f32(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__neon_p4()
159 const float r = vget_lane_f32(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__neon_p4()
Dsse-p8.c222 const __m128 vlr = _mm_add_ps(vtltr, _mm_mul_ps(vldrd, valphav)); in xnn_f32_ibilinear_chw_ukernel__sse_p8() local
225 const float l = _mm_cvtss_f32(vlr); in xnn_f32_ibilinear_chw_ukernel__sse_p8()
226 const float r = _mm_cvtss_f32(_mm_shuffle_ps(vlr, vlr, 1)); in xnn_f32_ibilinear_chw_ukernel__sse_p8()
Dwasmsimd-p8.c234 const v128_t vlr = wasm_f32x4_add(vtltr, wasm_f32x4_mul(vldrd, valphav)); in xnn_f32_ibilinear_chw_ukernel__wasmsimd_p8() local
237 const float l = wasm_f32x4_extract_lane(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__wasmsimd_p8()
238 const float r = wasm_f32x4_extract_lane(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__wasmsimd_p8()
Dneonfma-p8.c243 const float32x2_t vlr = vfma_f32(vtltr, vldrd, valphav); in xnn_f32_ibilinear_chw_ukernel__neonfma_p8() local
246 const float l = vget_lane_f32(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__neonfma_p8()
247 const float r = vget_lane_f32(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__neonfma_p8()
Dneon-p8.c243 const float32x2_t vlr = vmla_f32(vtltr, vldrd, valphav); in xnn_f32_ibilinear_chw_ukernel__neon_p8() local
246 const float l = vget_lane_f32(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__neon_p8()
247 const float r = vget_lane_f32(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__neon_p8()
Dneonfma-p16.c315 const float32x2_t vlr = vfma_f32(vtltr, vldrd, valphav); in xnn_f32_ibilinear_chw_ukernel__neonfma_p16() local
318 const float l = vget_lane_f32(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__neonfma_p16()
319 const float r = vget_lane_f32(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__neonfma_p16()
Dneon-p16.c315 const float32x2_t vlr = vmla_f32(vtltr, vldrd, valphav); in xnn_f32_ibilinear_chw_ukernel__neon_p16() local
318 const float l = vget_lane_f32(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__neon_p16()
319 const float r = vget_lane_f32(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__neon_p16()
/external/XNNPACK/src/f32-ibilinear-chw/
Dsse.c.in184 const __m128 vlr = _mm_add_ps(vtltr, _mm_mul_ps(vldrd, valphav)); variable
187 const float l = _mm_cvtss_f32(vlr);
188 const float r = _mm_cvtss_f32(_mm_shuffle_ps(vlr, vlr, 1));
Dwasmsimd.c.in188 const v128_t vlr = wasm_f32x4_add(vtltr, wasm_f32x4_mul(vldrd, valphav)); variable
191 const float l = wasm_f32x4_extract_lane(vlr, 0);
192 const float r = wasm_f32x4_extract_lane(vlr, 1);
Dneon.c.in193 const float32x2_t vlr = ${VMULADD_F32}(vtltr, vldrd, valphav);
196 const float l = vget_lane_f32(vlr, 0);
197 const float r = vget_lane_f32(vlr, 1);
/external/llvm/test/MC/SystemZ/
Dinsn-good-z13.s2415 #CHECK: vlr %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x56]
2416 #CHECK: vlr %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x56]
2417 #CHECK: vlr %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x56]
2418 #CHECK: vlr %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x56]
2419 #CHECK: vlr %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x56]
2420 #CHECK: vlr %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x56]
2422 vlr %v0, %v0
2423 vlr %v0, %v15
2424 vlr %v0, %v31
2425 vlr %v15, %v0
[all …]
Dinsn-bad-zEC12.s826 #CHECK: vlr %v0, %v0
828 vlr %v0, %v0
/external/cldr/tools/cldr-code/src/main/resources/org/unicode/cldr/util/data/
Diso-639-3_Retirements.tab159 vlr Vatrata S Split into Vera'a [vra] and Lemerig [lrz] 2009-01-16
/external/llvm/test/MC/Disassembler/SystemZ/
Dinsns-z13.txt1634 #CHECK: vlr %v0, %v0
1637 #CHECK: vlr %v19, %v14
1640 #CHECK: vlr %v31, %v31
/external/capstone/arch/SystemZ/
DSystemZGenInsnNameMaps.inc2007 { SYSZ_INS_VLR, "vlr" },
/external/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td16 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>;
/external/XNNPACK/src/amalgam/
Dsse.c5181 const __m128 vlr = _mm_add_ps(vtltr, _mm_mul_ps(vldrd, valphav)); in xnn_f32_ibilinear_chw_ukernel__sse_p8() local
5184 const float l = _mm_cvtss_f32(vlr); in xnn_f32_ibilinear_chw_ukernel__sse_p8()
5185 const float r = _mm_cvtss_f32(_mm_shuffle_ps(vlr, vlr, 1)); in xnn_f32_ibilinear_chw_ukernel__sse_p8()

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