| /external/llvm/test/MC/ARM/ |
| D | neon-satshift-encoding.s | 3 @ CHECK: vqshl.s8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xf2]
4 vqshl.s8 d16, d16, d17
5 @ CHECK: vqshl.s16 d16, d16, d17 @ encoding: [0xb0,0x04,0x51,0xf2]
6 vqshl.s16 d16, d16, d17
7 @ CHECK: vqshl.s32 d16, d16, d17 @ encoding: [0xb0,0x04,0x61,0xf2]
8 vqshl.s32 d16, d16, d17
9 @ CHECK: vqshl.s64 d16, d16, d17 @ encoding: [0xb0,0x04,0x71,0xf2]
10 vqshl.s64 d16, d16, d17
11 @ CHECK: vqshl.u8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xf3]
12 vqshl.u8 d16, d16, d17
[all …]
|
| D | neont2-satshift-encoding.s | 5 @ CHECK: vqshl.s8 d16, d16, d17 @ encoding: [0x41,0xef,0xb0,0x04]
6 vqshl.s8 d16, d16, d17
7 @ CHECK: vqshl.s16 d16, d16, d17 @ encoding: [0x51,0xef,0xb0,0x04]
8 vqshl.s16 d16, d16, d17
9 @ CHECK: vqshl.s32 d16, d16, d17 @ encoding: [0x61,0xef,0xb0,0x04]
10 vqshl.s32 d16, d16, d17
11 @ CHECK: vqshl.s64 d16, d16, d17 @ encoding: [0x71,0xef,0xb0,0x04]
12 vqshl.s64 d16, d16, d17
13 @ CHECK: vqshl.u8 d16, d16, d17 @ encoding: [0x41,0xff,0xb0,0x04]
14 vqshl.u8 d16, d16, d17
[all …]
|
| /external/capstone/suite/MC/ARM/ |
| D | neon-satshift-encoding.s.cs | 2 0xb0,0x04,0x41,0xf2 = vqshl.s8 d16, d16, d17
3 0xb0,0x04,0x51,0xf2 = vqshl.s16 d16, d16, d17
4 0xb0,0x04,0x61,0xf2 = vqshl.s32 d16, d16, d17
5 0xb0,0x04,0x71,0xf2 = vqshl.s64 d16, d16, d17
6 0xb0,0x04,0x41,0xf3 = vqshl.u8 d16, d16, d17
7 0xb0,0x04,0x51,0xf3 = vqshl.u16 d16, d16, d17
8 0xb0,0x04,0x61,0xf3 = vqshl.u32 d16, d16, d17
9 0xb0,0x04,0x71,0xf3 = vqshl.u64 d16, d16, d17
10 0xf0,0x04,0x42,0xf2 = vqshl.s8 q8, q8, q9
11 0xf0,0x04,0x52,0xf2 = vqshl.s16 q8, q8, q9
[all …]
|
| D | neont2-satshift-encoding.s.cs | 2 0x41,0xef,0xb0,0x04 = vqshl.s8 d16, d16, d17
3 0x51,0xef,0xb0,0x04 = vqshl.s16 d16, d16, d17
4 0x61,0xef,0xb0,0x04 = vqshl.s32 d16, d16, d17
5 0x71,0xef,0xb0,0x04 = vqshl.s64 d16, d16, d17
6 0x41,0xff,0xb0,0x04 = vqshl.u8 d16, d16, d17
7 0x51,0xff,0xb0,0x04 = vqshl.u16 d16, d16, d17
8 0x61,0xff,0xb0,0x04 = vqshl.u32 d16, d16, d17
9 0x71,0xff,0xb0,0x04 = vqshl.u64 d16, d16, d17
10 0x42,0xef,0xf0,0x04 = vqshl.s8 q8, q8, q9
11 0x52,0xef,0xf0,0x04 = vqshl.s16 q8, q8, q9
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vqshl.ll | 5 ;CHECK: vqshl.s8
14 ;CHECK: vqshl.s16
23 ;CHECK: vqshl.s32
32 ;CHECK: vqshl.s64
41 ;CHECK: vqshl.u8
50 ;CHECK: vqshl.u16
59 ;CHECK: vqshl.u32
68 ;CHECK: vqshl.u64
77 ;CHECK: vqshl.s8
86 ;CHECK: vqshl.s16
[all …]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 872 # CHECK: vqshl.s8 d16, d16, d17
874 # CHECK: vqshl.s16 d16, d16, d17
876 # CHECK: vqshl.s32 d16, d16, d17
878 # CHECK: vqshl.s64 d16, d16, d17
880 # CHECK: vqshl.u8 d16, d16, d17
882 # CHECK: vqshl.u16 d16, d16, d17
884 # CHECK: vqshl.u32 d16, d16, d17
886 # CHECK: vqshl.u64 d16, d16, d17
888 # CHECK: vqshl.s8 q8, q8, q9
890 # CHECK: vqshl.s16 q8, q8, q9
[all …]
|
| D | neon.txt | 983 # CHECK: vqshl.s8 d16, d16, d17
985 # CHECK: vqshl.s16 d16, d16, d17
987 # CHECK: vqshl.s32 d16, d16, d17
989 # CHECK: vqshl.s64 d16, d16, d17
991 # CHECK: vqshl.u8 d16, d16, d17
993 # CHECK: vqshl.u16 d16, d16, d17
995 # CHECK: vqshl.u32 d16, d16, d17
997 # CHECK: vqshl.u64 d16, d16, d17
999 # CHECK: vqshl.s8 q8, q8, q9
1001 # CHECK: vqshl.s16 q8, q8, q9
[all …]
|
| /external/arm-neon-tests/ |
| D | Makefile.gcc | 48 vst1_lane vqshl vqshl_n vqrshrn_n vsub vqadd vabs vqabs \
|
| D | ref_vqshl_n.c | 34 #define INSN vqshl
|
| D | Makefile | 42 vst1_lane vqshl vqshl_n vqrshrn_n vsub vqadd vabs vqabs \
|
| D | ref_vqshl.c | 34 #define INSN vqshl
|
| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 3748 { /* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $simm */
3751 { /* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $simm */
3754 { /* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $simm */
3757 { /* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $simm */
3760 { /* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $simm */
3763 { /* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $simm */
3766 { /* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $simm */
3769 { /* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $simm */
3796 { /* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $vn */
3799 { /* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $vn */
[all …]
|
| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 3748 { /* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $simm */
3751 { /* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $simm */
3754 { /* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $simm */
3757 { /* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $simm */
3760 { /* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $simm */
3763 { /* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $simm */
3766 { /* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $simm */
3769 { /* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $simm */
3796 { /* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $vn */
3799 { /* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $vn */
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9945 "unt\005vqshl\006vqshlu\006vqshrn\007vqshrnb\007vqshrnt\007vqshrun\010vq"
13960 …{ 3286 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON,…
13961 …{ 3286 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON…
13962 …{ 3286 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON,…
13963 …{ 3286 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON…
13964 …{ 3286 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON,…
13965 …{ 3286 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON…
13966 …{ 3286 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON,…
13967 …{ 3286 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON…
13968 …{ 3286 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON,…
[all …]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 5403 void vqshl(Condition cond,
5408 void vqshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { in vqshl() function
5409 vqshl(al, dt, rd, rm, operand); in vqshl()
5412 void vqshl(Condition cond,
5417 void vqshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { in vqshl() function
5418 vqshl(al, dt, rd, rm, operand); in vqshl()
|
| D | disasm-aarch32.h | 2248 void vqshl(Condition cond,
2254 void vqshl(Condition cond,
|
| D | disasm-aarch32.cc | 5946 void Disassembler::vqshl(Condition cond, in vqshl() function in vixl::aarch32::Disassembler
5960 void Disassembler::vqshl(Condition cond, in vqshl() function in vixl::aarch32::Disassembler
29788 vqshl(CurrentCond(), in DecodeT32()
30492 vqshl(CurrentCond(), in DecodeT32()
31593 vqshl(CurrentCond(), in DecodeT32()
36807 vqshl(CurrentCond(), in DecodeT32()
39926 vqshl(al, dt, DRegister(rd), DRegister(rm), DRegister(rn)); in DecodeA32()
39953 vqshl(al, dt, QRegister(rd), QRegister(rm), QRegister(rn)); in DecodeA32()
44155 vqshl(al, dt, DRegister(rd), DRegister(rm), imm); in DecodeA32()
48349 vqshl(al, dt, QRegister(rd), QRegister(rm), imm); in DecodeA32()
|
| D | assembler-aarch32.cc | 23436 void Assembler::vqshl(Condition cond, in vqshl() function in vixl::aarch32::Assembler
23502 Delegate(kVqshl, &Assembler::vqshl, cond, dt, rd, rm, operand); in vqshl()
23505 void Assembler::vqshl(Condition cond, in vqshl() function in vixl::aarch32::Assembler
23571 Delegate(kVqshl, &Assembler::vqshl, cond, dt, rd, rm, operand); in vqshl()
|
| D | macro-assembler-aarch32.h | 8891 vqshl(cond, dt, rd, rm, operand); in Vqshl()
8909 vqshl(cond, dt, rd, rm, operand); in Vqshl()
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 599 def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
1362 def SCALAR_QSHL: SInst<"vqshl", "sss", "ScSsSiSlSUcSUsSUiSUl">;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrMVE.td | 2744 defm MVE_VQSHL_by_vec : mve_shift_by_vec_multi<"vqshl", 0b1, 0b0>;
2852 : MVE_shift_with_imm<"vqshl", VTI_.Suffix, (outs MQPR:$Qd),
4562 defm MVE_VQSHL_qr : MVE_VxSHL_qr_types<"vqshl", 0b1, 0b0>;
|
| D | ARMInstrNEON.td | 5965 "vqshl", "s", int_arm_neon_vqshifts>;
5968 "vqshl", "u", int_arm_neon_vqshiftu>;
5970 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshlsImm>;
5971 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshluImm>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 5497 "vqshl", "s", int_arm_neon_vqshifts>;
5500 "vqshl", "u", int_arm_neon_vqshiftu>;
5502 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
5503 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicImpl.inc | 1653 "llvm.arm.mve.vqshl.imm",
1654 "llvm.arm.mve.vqshl.imm.predicated",
11786 1, // llvm.arm.mve.vqshl.imm
11787 1, // llvm.arm.mve.vqshl.imm.predicated
|