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Searched refs:vtbl (Results 1 – 25 of 150) sorted by relevance

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/external/mesa3d/src/gallium/drivers/iris/
Diris_perf.c48 batch->screen->vtbl.emit_mi_report_perf_count(batch, bo, offset_in_bytes, report_id); in iris_perf_emit_mi_report_perf_count()
66 batch->screen->vtbl.store_register_mem64(batch, reg, bo, offset, false); in iris_perf_store_register_mem()
69 batch->screen->vtbl.store_register_mem32(batch, reg, bo, offset, false); in iris_perf_store_register_mem()
88 perf_cfg->vtbl.bo_alloc = iris_oa_bo_alloc; in iris_perf_init_vtbl()
89 perf_cfg->vtbl.bo_unreference = (bo_unreference_t)iris_bo_unreference; in iris_perf_init_vtbl()
90 perf_cfg->vtbl.bo_map = (bo_map_t)iris_bo_map; in iris_perf_init_vtbl()
91 perf_cfg->vtbl.bo_unmap = (bo_unmap_t)iris_bo_unmap; in iris_perf_init_vtbl()
92 perf_cfg->vtbl.emit_stall_at_pixel_scoreboard = in iris_perf_init_vtbl()
95 perf_cfg->vtbl.emit_mi_report_perf_count = in iris_perf_init_vtbl()
97 perf_cfg->vtbl.batchbuffer_flush = iris_perf_batchbuffer_flush; in iris_perf_init_vtbl()
[all …]
/external/mesa3d/src/gallium/auxiliary/util/
Du_transfer_helper.c35 const struct u_transfer_vtbl *vtbl; member
46 if (helper->vtbl->get_internal_format) { in handle_transfer()
48 helper->vtbl->get_internal_format(prsc); in handle_transfer()
99 prsc = helper->vtbl->resource_create(pscreen, &t); in u_transfer_helper_resource_create()
106 stencil = helper->vtbl->resource_create(pscreen, &t); in u_transfer_helper_resource_create()
109 helper->vtbl->resource_destroy(pscreen, prsc); in u_transfer_helper_resource_create()
113 helper->vtbl->set_stencil(prsc, stencil); in u_transfer_helper_resource_create()
119 prsc = helper->vtbl->resource_create(pscreen, &t); in u_transfer_helper_resource_create()
126 prsc = helper->vtbl->resource_create(pscreen, templ); in u_transfer_helper_resource_create()
140 if (helper->vtbl->get_stencil) { in u_transfer_helper_resource_destroy()
[all …]
/external/rust/crates/ring/pregenerated/
Dvpaes-armv7-linux32.S113 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1
114 vtbl.8 d3, {q2}, d3
115 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2
116 vtbl.8 d5, {q3}, d1
129 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u
130 vtbl.8 d9, {q13}, d5
132 vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t
133 vtbl.8 d1, {q12}, d7
135 vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
136 vtbl.8 d11, {q15}, d5
[all …]
/external/openscreen/third_party/boringssl/ios-arm/crypto/fipsmodule/
Dvpaes-armv7.S118 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1
119 vtbl.8 d3, {q2}, d3
120 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2
121 vtbl.8 d5, {q3}, d1
134 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u
135 vtbl.8 d9, {q13}, d5
137 vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t
138 vtbl.8 d1, {q12}, d7
140 vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
141 vtbl.8 d11, {q15}, d5
[all …]
/external/rust/crates/quiche/deps/boringssl/ios-arm/crypto/fipsmodule/
Dvpaes-armv7.S118 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1
119 vtbl.8 d3, {q2}, d3
120 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2
121 vtbl.8 d5, {q3}, d1
134 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u
135 vtbl.8 d9, {q13}, d5
137 vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t
138 vtbl.8 d1, {q12}, d7
140 vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
141 vtbl.8 d11, {q15}, d5
[all …]
/external/cronet/third_party/boringssl/apple-arm/crypto/fipsmodule/
Dvpaes-armv7-apple.S118 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1
119 vtbl.8 d3, {q2}, d3
120 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2
121 vtbl.8 d5, {q3}, d1
134 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u
135 vtbl.8 d9, {q13}, d5
137 vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t
138 vtbl.8 d1, {q12}, d7
140 vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
141 vtbl.8 d11, {q15}, d5
[all …]
/external/boringssl/apple-arm/crypto/fipsmodule/
Dvpaes-armv7-apple.S118 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1
119 vtbl.8 d3, {q2}, d3
120 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2
121 vtbl.8 d5, {q3}, d1
134 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u
135 vtbl.8 d9, {q13}, d5
137 vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t
138 vtbl.8 d1, {q12}, d7
140 vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
141 vtbl.8 d11, {q15}, d5
[all …]
/external/openscreen/third_party/boringssl/linux-arm/crypto/fipsmodule/
Dvpaes-armv7.S115 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1
116 vtbl.8 d3, {q2}, d3
117 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2
118 vtbl.8 d5, {q3}, d1
131 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u
132 vtbl.8 d9, {q13}, d5
134 vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t
135 vtbl.8 d1, {q12}, d7
137 vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
138 vtbl.8 d11, {q15}, d5
[all …]
/external/boringssl/linux-arm/crypto/fipsmodule/
Dvpaes-armv7-linux.S114 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1
115 vtbl.8 d3, {q2}, d3
116 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2
117 vtbl.8 d5, {q3}, d1
130 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u
131 vtbl.8 d9, {q13}, d5
133 vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t
134 vtbl.8 d1, {q12}, d7
136 vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
137 vtbl.8 d11, {q15}, d5
[all …]
/external/rust/crates/quiche/deps/boringssl/linux-arm/crypto/fipsmodule/
Dvpaes-armv7.S115 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1
116 vtbl.8 d3, {q2}, d3
117 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2
118 vtbl.8 d5, {q3}, d1
131 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u
132 vtbl.8 d9, {q13}, d5
134 vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t
135 vtbl.8 d1, {q12}, d7
137 vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
138 vtbl.8 d11, {q15}, d5
[all …]
/external/cronet/third_party/boringssl/linux-arm/crypto/fipsmodule/
Dvpaes-armv7-linux.S114 vtbl.8 d2, {q2}, d2 @ vpshufb %xmm1, %xmm2, %xmm1
115 vtbl.8 d3, {q2}, d3
116 vtbl.8 d4, {q3}, d0 @ vpshufb %xmm0, %xmm3, %xmm2
117 vtbl.8 d5, {q3}, d1
130 vtbl.8 d8, {q13}, d4 @ vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u
131 vtbl.8 d9, {q13}, d5
133 vtbl.8 d0, {q12}, d6 @ vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t
134 vtbl.8 d1, {q12}, d7
136 vtbl.8 d10, {q15}, d4 @ vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
137 vtbl.8 d11, {q15}, d5
[all …]
/external/llvm/test/MC/ARM/
Dneon-table-encoding.s3 vtbl.8 d16, {d17}, d16
4 vtbl.8 d16, {d16, d17}, d18
5 vtbl.8 d16, {d16, d17, d18}, d20
6 vtbl.8 d16, {d16, d17, d18, d19}, d20
8 @ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3]
9 @ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3]
10 @ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3]
11 @ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3]
Dneont2-table-encoding.s5 vtbl.8 d16, {d17}, d16
6 vtbl.8 d16, {d16, d17}, d18
7 vtbl.8 d16, {d16, d17, d18}, d20
8 vtbl.8 d16, {d16, d17, d18, d19}, d20
10 @ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xf1,0xff,0xa0,0x08]
11 @ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xf0,0xff,0xa2,0x09]
12 @ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xf0,0xff,0xa4,0x0a]
13 @ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xf0,0xff,0xa4,0x0b]
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.c59 brw->vtbl.emit_raw_pipe_control(brw, flags, NULL, 0, 0); in brw_emit_pipe_control_flush()
75 brw->vtbl.emit_raw_pipe_control(brw, flags, bo, offset, imm); in brw_emit_pipe_control_write()
171 brw->vtbl.emit_raw_pipe_control(brw, in gen7_emit_isp_disable()
175 brw->vtbl.emit_raw_pipe_control(brw, in gen7_emit_isp_disable()
401 brw->vtbl.emit_raw_pipe_control = gen11_emit_raw_pipe_control; in brw_init_pipe_control()
404 brw->vtbl.emit_raw_pipe_control = gen9_emit_raw_pipe_control; in brw_init_pipe_control()
407 brw->vtbl.emit_raw_pipe_control = gen8_emit_raw_pipe_control; in brw_init_pipe_control()
410 brw->vtbl.emit_raw_pipe_control = in brw_init_pipe_control()
415 brw->vtbl.emit_raw_pipe_control = gen6_emit_raw_pipe_control; in brw_init_pipe_control()
418 brw->vtbl.emit_raw_pipe_control = gen5_emit_raw_pipe_control; in brw_init_pipe_control()
[all …]
Dbrw_performance_query.c429 ctx->vtbl.emit_mi_report_perf_count(ctx, in brw_oa_emit_mi_report_perf_count()
492 perf_cfg->vtbl.bo_alloc = brw_oa_bo_alloc; in brw_init_perf_query_info()
493 perf_cfg->vtbl.bo_unreference = (bo_unreference_t)brw_bo_unreference; in brw_init_perf_query_info()
494 perf_cfg->vtbl.bo_map = (bo_map_t)brw_bo_map; in brw_init_perf_query_info()
495 perf_cfg->vtbl.bo_unmap = (bo_unmap_t)brw_bo_unmap; in brw_init_perf_query_info()
496 perf_cfg->vtbl.emit_stall_at_pixel_scoreboard = in brw_init_perf_query_info()
498 perf_cfg->vtbl.emit_mi_report_perf_count = in brw_init_perf_query_info()
500 perf_cfg->vtbl.batchbuffer_flush = brw_oa_batchbuffer_flush; in brw_init_perf_query_info()
501 perf_cfg->vtbl.store_register_mem = in brw_init_perf_query_info()
503 perf_cfg->vtbl.batch_references = (batch_references_t)brw_batch_references; in brw_init_perf_query_info()
[all …]
/external/mesa3d/src/gallium/auxiliary/pipebuffer/
Dpb_buffer.h124 const struct pb_vtbl *vtbl; member
180 return buf->vtbl->map(buf, flags, flush_ctx); in pb_map()
191 buf->vtbl->unmap(buf); in pb_unmap()
207 assert(buf->vtbl->get_base_buffer); in pb_get_base_buffer()
208 buf->vtbl->get_base_buffer(buf, base_buf, offset); in pb_get_base_buffer()
221 assert(buf->vtbl->validate); in pb_validate()
222 return buf->vtbl->validate(buf, vl, flags); in pb_validate()
232 assert(buf->vtbl->fence); in pb_fence()
233 buf->vtbl->fence(buf, fence); in pb_fence()
244 buf->vtbl->destroy(buf); in pb_destroy()
/external/libhevc/common/arm/
Dihevc_intra_pred_luma_mode_3_to_9.s205 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 0)
208 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 0)
212 vtbl.8 d16, {d0,d1}, d4 @load from ref_main_idx (row 1)
216 vtbl.8 d17, {d0,d1}, d5 @load from ref_main_idx + 1 (row 1)
222 vtbl.8 d14, {d0,d1}, d8 @load from ref_main_idx (row 2)
226 vtbl.8 d15, {d0,d1}, d9 @load from ref_main_idx + 1 (row 2)
233 vtbl.8 d10, {d0,d1}, d4 @load from ref_main_idx (row 3)
237 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx + 1 (row 3)
244 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 4)
248 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 4)
[all …]
Dihevc_intra_pred_filters_luma_mode_11_to_17.s315 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 0)
318 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 0)
322 vtbl.8 d16, {d0,d1}, d4 @load from ref_main_idx (row 1)
326 vtbl.8 d17, {d0,d1}, d5 @load from ref_main_idx + 1 (row 1)
332 vtbl.8 d14, {d0,d1}, d8 @load from ref_main_idx (row 2)
336 vtbl.8 d15, {d0,d1}, d9 @load from ref_main_idx + 1 (row 2)
343 vtbl.8 d10, {d0,d1}, d4 @load from ref_main_idx (row 3)
347 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx + 1 (row 3)
354 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 4)
358 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 4)
[all …]
Dihevc_intra_pred_chroma_mode_3_to_9.s201 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 0)
204 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 0)
210 vtbl.8 d16, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 1)
214 vtbl.8 d17, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 1)
220 vtbl.8 d14, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 2)
224 vtbl.8 d15, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 2)
231 vtbl.8 d10, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 3)
235 vtbl.8 d11, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 3)
242 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 4)
246 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 4)
[all …]
Dihevc_intra_pred_filters_chroma_mode_11_to_17.s314 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 0)
317 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 0)
324 vtbl.8 d16, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 1)
328 vtbl.8 d17, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 1)
334 vtbl.8 d14, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 2)
338 vtbl.8 d15, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 2)
345 vtbl.8 d10, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 3)
349 vtbl.8 d11, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 3)
356 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 4)
360 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 4)
[all …]
/external/mesa3d/src/intel/perf/
Dgen_perf_query.c626 perf->vtbl.store_register_mem(ctx->ctx, obj->pipeline_stats.bo, in snapshot_statistics_registers()
641 perf->vtbl.store_register_mem(ctx->ctx, query->oa.bo, GEN7_RPSTAT1, 4, bo_offset); in snapshot_freq_register()
643 perf->vtbl.store_register_mem(ctx->ctx, query->oa.bo, GEN9_RPSTAT0, 4, bo_offset); in snapshot_freq_register()
691 perf_cfg->vtbl.emit_stall_at_pixel_scoreboard(perf_ctx->ctx); in gen_perf_begin_query()
787 perf_cfg->vtbl.bo_unreference(query->oa.bo); in gen_perf_begin_query()
791 query->oa.bo = perf_cfg->vtbl.bo_alloc(perf_ctx->bufmgr, in gen_perf_begin_query()
796 void *map = perf_cfg->vtbl.bo_map(perf_ctx->ctx, query->oa.bo, MAP_WRITE); in gen_perf_begin_query()
798 perf_cfg->vtbl.bo_unmap(query->oa.bo); in gen_perf_begin_query()
805 perf_cfg->vtbl.emit_mi_report_perf_count(perf_ctx->ctx, query->oa.bo, 0, in gen_perf_begin_query()
837 perf_cfg->vtbl.bo_unreference(query->pipeline_stats.bo); in gen_perf_begin_query()
[all …]
/external/OpenCL-CTS/test_conformance/math_brute_force/
Dfunction_list.cpp107 static constexpr vtbl _unary = {
113 static constexpr vtbl _i_unary = {
119 static constexpr vtbl _unary_u = {
125 static constexpr vtbl _macro_unary = {
131 static constexpr vtbl _binary = {
137 static constexpr vtbl _binary_operator = {
143 static constexpr vtbl _binary_i = {
149 static constexpr vtbl _macro_binary = {
155 static constexpr vtbl _ternary = {
161 static constexpr vtbl _unary_two_results = {
[all …]
/external/capstone/suite/MC/ARM/
Dneon-table-encoding.s.cs2 0xa0,0x08,0xf1,0xf3 = vtbl.8 d16, {d17}, d16
3 0xa2,0x09,0xf0,0xf3 = vtbl.8 d16, {d16, d17}, d18
4 0xa4,0x0a,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18}, d20
5 0xa4,0x0b,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18, d19}, d20
Dneont2-table-encoding.s.cs2 0xf1,0xff,0xa0,0x08 = vtbl.8 d16, {d17}, d16
3 0xf0,0xff,0xa2,0x09 = vtbl.8 d16, {d16, d17}, d18
4 0xf0,0xff,0xa4,0x0a = vtbl.8 d16, {d16, d17, d18}, d20
5 0xf0,0xff,0xa4,0x0b = vtbl.8 d16, {d16, d17, d18, d19}, d20
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_context.c125 radeon->vtbl.swtcl_flush = r100_swtcl_flush; in r100_init_vtbl()
126 radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state; in r100_init_vtbl()
127 radeon->vtbl.fallback = radeonFallback; in r100_init_vtbl()
128 radeon->vtbl.free_context = r100_vtbl_free_context; in r100_init_vtbl()
129 radeon->vtbl.emit_query_finish = r100_emit_query_finish; in r100_init_vtbl()
130 radeon->vtbl.check_blit = r100_check_blit; in r100_init_vtbl()
131 radeon->vtbl.blit = r100_blit; in r100_init_vtbl()
132 radeon->vtbl.is_format_renderable = radeonIsFormatRenderable; in r100_init_vtbl()
133 radeon->vtbl.revalidate_all_buffers = r100ValidateBuffers; in r100_init_vtbl()

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