| /external/vixl/examples/aarch64/ |
| D | neon-matrix-multiply.cc | 54 __ Fmul(v_out, v4.V4S(), v_in, 0); // e.g. (v0.V4S(), v4.V4S(), v8.S(), 0). in GenerateMultiplyColumn() local
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| /external/vixl/test/aarch64/ |
| D | test-assembler-fp-aarch64.cc | 634 __ Fmul(s0, s17, s18); in TEST() local
635 __ Fmul(s1, s18, s19); in TEST() local
636 __ Fmul(s2, s14, s14); in TEST() local
637 __ Fmul(s3, s15, s20); in TEST() local
638 __ Fmul(s4, s16, s20); in TEST() local
639 __ Fmul(s5, s15, s19); in TEST() local
640 __ Fmul(s6, s19, s16); in TEST() local
642 __ Fmul(d7, d30, d31); in TEST() local
643 __ Fmul(d8, d29, d31); in TEST() local
644 __ Fmul(d9, d26, d26); in TEST() local
[all …]
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| D | test-assembler-sve-aarch64.cc | 14825 __ Fmul(z2.VnH(), z1.VnH(), z0.VnH(), 0); in TEST_SVE() local
14826 __ Fmul(z3.VnH(), z1.VnH(), z0.VnH(), 1); in TEST_SVE() local
14827 __ Fmul(z4.VnH(), z1.VnH(), z0.VnH(), 4); in TEST_SVE() local
14828 __ Fmul(z5.VnH(), z1.VnH(), z0.VnH(), 7); in TEST_SVE() local
14830 __ Fmul(z6.VnS(), z1.VnS(), z0.VnS(), 0); in TEST_SVE() local
14831 __ Fmul(z7.VnS(), z1.VnS(), z0.VnS(), 1); in TEST_SVE() local
14832 __ Fmul(z8.VnS(), z1.VnS(), z0.VnS(), 2); in TEST_SVE() local
14833 __ Fmul(z9.VnS(), z1.VnS(), z0.VnS(), 3); in TEST_SVE() local
14835 __ Fmul(z10.VnD(), z1.VnD(), z0.VnD(), 0); in TEST_SVE() local
14836 __ Fmul(z11.VnD(), z1.VnD(), z0.VnD(), 1); in TEST_SVE() local
[all …]
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| D | test-utils-aarch64.cc | 854 __ Fmul(z31.WithLaneSize(esize), in SetFpData() local
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| D | test-assembler-neon-aarch64.cc | 3773 __ Fmul(v6.V4H(), v1.V4H(), v0.V4H()); in TEST() local
3774 __ Fmul(v7.V8H(), v3.V8H(), v2.V8H()); in TEST() local
3775 __ Fmul(v8.V4H(), v4.V4H(), v3.V4H()); in TEST() local
3776 __ Fmul(v9.V4H(), v0.V4H(), v1.V4H()); in TEST() local
3777 __ Fmul(v10.V4H(), v5.V4H(), v0.V4H()); in TEST() local
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| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 367 __ Fmul(PickV(size), PickV(size), PickV(size)); in GenerateFPSequence() local
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-sve-aarch64.cc | 733 void MacroAssembler::Fmul(const ZRegister& zd, in Fmul() function in vixl::aarch64::MacroAssembler
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| D | macro-assembler-aarch64.h | 1624 void Fmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) { in Fmul() function
4529 void Fmul(const ZRegister& zd, in Fmul() function
4542 void Fmul(const ZRegister& zd, in Fmul() function
4550 void Fmul(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Fmul() function
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2411 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); in ExpandLegalINT_TO_FP() local
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