| /external/vixl/test/aarch64/ |
| D | test-simulator-traces-aarch64.h | 29 // test-simulator-aarch64.
31 // If you update input lists in test-simulator-inputs-aarch64.h, or add a new
32 // test to test-simulator-aarch64.cc, please run
44 // To add a new simulator test to test-simulator-aarch64.cc, add placeholder
45 // array(s) below to build test-simulator-aarch64 for reference platform. Then,
63 #include "aarch64/traces/sim-abs-16b-trace-aarch64.h"
64 #include "aarch64/traces/sim-abs-2d-trace-aarch64.h"
65 #include "aarch64/traces/sim-abs-2s-trace-aarch64.h"
66 #include "aarch64/traces/sim-abs-4h-trace-aarch64.h"
67 #include "aarch64/traces/sim-abs-4s-trace-aarch64.h"
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| /external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicsAArch64.h | 16 aarch64_addg = 268, // llvm.aarch64.addg
17 aarch64_clrex, // llvm.aarch64.clrex
18 aarch64_cls, // llvm.aarch64.cls
19 aarch64_cls64, // llvm.aarch64.cls64
20 aarch64_crc32b, // llvm.aarch64.crc32b
21 aarch64_crc32cb, // llvm.aarch64.crc32cb
22 aarch64_crc32ch, // llvm.aarch64.crc32ch
23 aarch64_crc32cw, // llvm.aarch64.crc32cw
24 aarch64_crc32cx, // llvm.aarch64.crc32cx
25 aarch64_crc32h, // llvm.aarch64.crc32h
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
33 #define DEBUG_TYPE "aarch64-disassembler"
305 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
306 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
307 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
308 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
309 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
310 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
311 AArch64::Q30, AArch64::Q31
334 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -------*- C++ -*-===//
26 #define DEBUG_TYPE "aarch64-disassembler"
256 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
257 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
258 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
259 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
260 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
261 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
262 AArch64::Q30, AArch64::Q31
285 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
10 // the AArch64 target useful for the compiler back-end and the MC libraries.
21 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
31 case AArch64::X0: return AArch64::W0; in getWRegFromXReg()
32 case AArch64::X1: return AArch64::W1; in getWRegFromXReg()
33 case AArch64::X2: return AArch64::W2; in getWRegFromXReg()
34 case AArch64::X3: return AArch64::W3; in getWRegFromXReg()
35 case AArch64::X4: return AArch64::W4; in getWRegFromXReg()
36 case AArch64::X5: return AArch64::W5; in getWRegFromXReg()
37 case AArch64::X6: return AArch64::W6; in getWRegFromXReg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FalkorHWPFFix.cpp | 15 #include "AArch64.h"
247 case AArch64::LD1i64: in getLoadInfo()
248 case AArch64::LD2i64: in getLoadInfo()
255 case AArch64::LD1i8: in getLoadInfo()
256 case AArch64::LD1i16: in getLoadInfo()
257 case AArch64::LD1i32: in getLoadInfo()
258 case AArch64::LD2i8: in getLoadInfo()
259 case AArch64::LD2i16: in getLoadInfo()
260 case AArch64::LD2i32: in getLoadInfo()
261 case AArch64::LD3i8: in getLoadInfo()
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| D | AArch64MacroFusion.cpp | 1 //===- AArch64MacroFusion.cpp - AArch64 Macro Fusion ----------------------===//
9 /// \file This file contains the AArch64 implementation of the DAG scheduling
25 if (SecondMI.getOpcode() != AArch64::Bcc) in isArithmeticBccPair()
33 case AArch64::ADDSWri: in isArithmeticBccPair()
34 case AArch64::ADDSWrr: in isArithmeticBccPair()
35 case AArch64::ADDSXri: in isArithmeticBccPair()
36 case AArch64::ADDSXrr: in isArithmeticBccPair()
37 case AArch64::ANDSWri: in isArithmeticBccPair()
38 case AArch64::ANDSWrr: in isArithmeticBccPair()
39 case AArch64::ANDSXri: in isArithmeticBccPair()
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| D | AArch64InstrInfo.cpp | 1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
58 "aarch64-tbz-offset-bits", cl::Hidden, cl::init(14),
62 "aarch64-cbz-offset-bits", cl::Hidden, cl::init(19),
66 BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19),
70 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP, in AArch64InstrInfo()
71 AArch64::CATCHRET), in AArch64InstrInfo()
83 if (Op == AArch64::INLINEASM || Op == AArch64::INLINEASM_BR) in getInstSizeInBytes()
110 case AArch64::TLSDESC_CALLSEQ: in getInstSizeInBytes()
114 case AArch64::JumpTableDest32: in getInstSizeInBytes()
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| D | AArch64PBQPRegAlloc.cpp | 1 //===-- AArch64PBQPRegAlloc.cpp - AArch64 specific PBQP constraints -------===//
8 // This file contains the AArch64 / Cortex-A57 specific register allocation
17 #define DEBUG_TYPE "aarch64-pbqp"
20 #include "AArch64.h"
37 return AArch64::FPR32RegClass.contains(reg) || in isFPReg()
38 AArch64::FPR64RegClass.contains(reg) || in isFPReg()
39 AArch64::FPR128RegClass.contains(reg); in isFPReg()
47 case AArch64::S1: in isOdd()
48 case AArch64::S3: in isOdd()
49 case AArch64::S5: in isOdd()
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| D | AArch64SIMDInstrOpt.cpp | 56 #define DEBUG_TYPE "aarch64-simdinstr-opt"
62 "AArch64 SIMD instructions optimization pass"
103 RuleST2(AArch64::ST2Twov2d, AArch64::ZIP1v2i64, AArch64::ZIP2v2i64,
104 AArch64::STPQi, AArch64::FPR128RegClass),
105 RuleST2(AArch64::ST2Twov4s, AArch64::ZIP1v4i32, AArch64::ZIP2v4i32,
106 AArch64::STPQi, AArch64::FPR128RegClass),
107 RuleST2(AArch64::ST2Twov2s, AArch64::ZIP1v2i32, AArch64::ZIP2v2i32,
108 AArch64::STPDi, AArch64::FPR64RegClass),
109 RuleST2(AArch64::ST2Twov8h, AArch64::ZIP1v8i16, AArch64::ZIP2v8i16,
110 AArch64::STPQi, AArch64::FPR128RegClass),
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| D | AArch64CondBrTuning.cpp | 1 //===-- AArch64CondBrTuning.cpp --- Conditional branch tuning for AArch64 -===//
28 #include "AArch64.h"
43 #define DEBUG_TYPE "aarch64-cond-br-tuning"
44 #define AARCH64_CONDBR_TUNING_NAME "AArch64 Conditional Branch Tuning"
72 INITIALIZE_PASS(AArch64CondBrTuning, "aarch64-cond-br-tuning",
94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV) in convertToFlagSetting()
103 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in convertToFlagSetting()
120 case AArch64::CBZW: in convertToCondBr()
121 case AArch64::CBZX: in convertToCondBr()
124 case AArch64::CBNZW: in convertToCondBr()
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
11 // the AArch64 target useful for the compiler back-end and the MC libraries.
22 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
32 case AArch64::X0: return AArch64::W0; in getWRegFromXReg()
33 case AArch64::X1: return AArch64::W1; in getWRegFromXReg()
34 case AArch64::X2: return AArch64::W2; in getWRegFromXReg()
35 case AArch64::X3: return AArch64::W3; in getWRegFromXReg()
36 case AArch64::X4: return AArch64::W4; in getWRegFromXReg()
37 case AArch64::X5: return AArch64::W5; in getWRegFromXReg()
38 case AArch64::X6: return AArch64::W6; in getWRegFromXReg()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | AArch64TargetParser.def | 1 //===- AARCH64TargetParser.def - AARCH64 target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the AARCH64 target parser's logic.
19 ARMBuildAttrs::CPUArch::v8_A, FK_NONE, AArch64::AEK_NONE)
22 (AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD))
25 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
26 AArch64::AEK_SIMD | AArch64::AEK_LSE | AArch64::AEK_RDM))
29 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
30 AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
31 AArch64::AEK_RDM))
34 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
[all …]
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenCallingConv.inc | 90 AArch64::X0, AArch64::X1
93 AArch64::W0, AArch64::W1
106 if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
119 if (unsigned Reg = State.AllocateReg(AArch64::X18)) {
127 if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
136 if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
159 …AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64…
186 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
216 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
219 …AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64…
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| D | AArch64GenMCCodeEmitter.inc | 5407 case AArch64::ADDSWrr:
5408 case AArch64::ADDSXrr:
5409 case AArch64::ADDWrr:
5410 case AArch64::ADDXrr:
5411 case AArch64::ADDlowTLS:
5412 case AArch64::ADJCALLSTACKDOWN:
5413 case AArch64::ADJCALLSTACKUP:
5414 case AArch64::AESIMCrrTied:
5415 case AArch64::AESMCrrTied:
5416 case AArch64::ANDSWrr:
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| D | AArch64GenRegisterInfo.inc | 18 namespace AArch64 {
651 } // end namespace AArch64
655 namespace AArch64 {
767 } // end namespace AArch64
772 namespace AArch64 {
779 } // end namespace AArch64
784 namespace AArch64 {
888 } // end namespace AArch64
2160 { AArch64::FFR },
2161 { AArch64::W29 },
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
36 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP), in AArch64InstrInfo()
46 if (MI.getOpcode() == AArch64::INLINEASM) in GetInstSizeInBytes()
70 case AArch64::Bcc: in parseCondBranch()
74 case AArch64::CBZW: in parseCondBranch()
75 case AArch64::CBZX: in parseCondBranch()
76 case AArch64::CBNZW: in parseCondBranch()
77 case AArch64::CBNZX: in parseCondBranch()
83 case AArch64::TBZW: in parseCondBranch()
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| D | AArch64PBQPRegAlloc.cpp | 1 //===-- AArch64PBQPRegAlloc.cpp - AArch64 specific PBQP constraints -------===//
9 // This file contains the AArch64 / Cortex-A57 specific register allocation
18 #define DEBUG_TYPE "aarch64-pbqp"
20 #include "AArch64.h"
38 return AArch64::FPR32RegClass.contains(reg) || in isFPReg()
39 AArch64::FPR64RegClass.contains(reg) || in isFPReg()
40 AArch64::FPR128RegClass.contains(reg); in isFPReg()
48 case AArch64::S1: in isOdd()
49 case AArch64::S3: in isOdd()
50 case AArch64::S5: in isOdd()
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| D | AArch64LoadStoreOptimizer.cpp | 1 //=- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -*- C++ -*-=//
34 #define DEBUG_TYPE "aarch64-ldst-opt"
46 static cl::opt<unsigned> LdStLimit("aarch64-load-store-scan-limit",
51 static cl::opt<unsigned> UpdateLimit("aarch64-update-scan-limit", cl::init(100),
62 #define AARCH64_LOAD_STORE_OPT_NAME "AArch64 load / store optimization pass"
179 INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
186 case AArch64::LDRBBui: in getBitExtrOpcode()
187 case AArch64::LDURBBi: in getBitExtrOpcode()
188 case AArch64::LDRHHui: in getBitExtrOpcode()
189 case AArch64::LDURHHi: in getBitExtrOpcode()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64InstPrinter.cpp | 1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
9 // This class prints an AArch64 MCInst to a .s file.
66 if (Opcode == AArch64::SYSxt) in printInst()
73 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || in printInst()
74 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { in printInst()
80 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); in printInst()
81 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri); in printInst()
123 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
126 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && in printInst()
130 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { in printInst()
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| D | AArch64MCTargetDesc.cpp | 1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
9 // This file provides AArch64 specific target descriptions.
65 {codeview::RegisterId::ARM64_W0, AArch64::W0}, in initLLVMToCVRegMapping()
66 {codeview::RegisterId::ARM64_W1, AArch64::W1}, in initLLVMToCVRegMapping()
67 {codeview::RegisterId::ARM64_W2, AArch64::W2}, in initLLVMToCVRegMapping()
68 {codeview::RegisterId::ARM64_W3, AArch64::W3}, in initLLVMToCVRegMapping()
69 {codeview::RegisterId::ARM64_W4, AArch64::W4}, in initLLVMToCVRegMapping()
70 {codeview::RegisterId::ARM64_W5, AArch64::W5}, in initLLVMToCVRegMapping()
71 {codeview::RegisterId::ARM64_W6, AArch64::W6}, in initLLVMToCVRegMapping()
72 {codeview::RegisterId::ARM64_W7, AArch64::W7}, in initLLVMToCVRegMapping()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
10 // This class prints an AArch64 MCInst to a .s file.
58 if (Opcode == AArch64::SYSxt) in printInst()
65 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || in printInst()
66 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { in printInst()
72 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); in printInst()
73 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri); in printInst()
115 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
118 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && in printInst()
122 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { in printInst()
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| /external/swiftshader/third_party/llvm-subzero/include/llvm/Support/ |
| D | AArch64TargetParser.def | 1 //===- AARCH64TargetParser.def - AARCH64 target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the AARCH64 target parser's logic.
20 ARMBuildAttrs::CPUArch::v8_A, FK_NONE, AArch64::AEK_NONE)
23 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
24 AArch64::AEK_SIMD | AArch64::AEK_LSE))
27 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
28 AArch64::AEK_SIMD | AArch64::AEK_LSE))
31 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
32 AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE))
39 AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr)
[all …]
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| /external/llvm/include/llvm/Support/ |
| D | AArch64TargetParser.def | 1 //===- AARCH64TargetParser.def - AARCH64 target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the AARCH64 target parser's logic.
20 ARMBuildAttrs::CPUArch::v8_A, FK_NONE, AArch64::AEK_NONE)
23 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
24 AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_PROFILE))
27 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
28 AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_PROFILE))
31 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
32 AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_PROFILE |
33 AArch64::AEK_RAS))
[all …]
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| /external/XNNPACK/test/ |
| D | f16-dwconv2d-chw.yaml | 10 - aarch64
14 - aarch64
18 - aarch64
22 - aarch64
26 - aarch64
30 - aarch64
34 - aarch64
38 - aarch64
42 - aarch64
46 - aarch64
[all …]
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