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Searched refs:ARM_INS_VSHR (Results 1 – 7 of 7) sorted by relevance

/external/capstone/arch/ARM/
DARMMappingInsn.inc8879 ARM_VSHRsv16i8, ARM_INS_VSHR,
8885 ARM_VSHRsv1i64, ARM_INS_VSHR,
8891 ARM_VSHRsv2i32, ARM_INS_VSHR,
8897 ARM_VSHRsv2i64, ARM_INS_VSHR,
8903 ARM_VSHRsv4i16, ARM_INS_VSHR,
8909 ARM_VSHRsv4i32, ARM_INS_VSHR,
8915 ARM_VSHRsv8i16, ARM_INS_VSHR,
8921 ARM_VSHRsv8i8, ARM_INS_VSHR,
8927 ARM_VSHRuv16i8, ARM_INS_VSHR,
8933 ARM_VSHRuv1i64, ARM_INS_VSHR,
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DARMMappingInsnOp.inc4441 { /* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr${p}.s8 $vd, $vm, $simm */
4444 { /* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr${p}.s64 $vd, $vm, $simm */
4447 { /* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr${p}.s32 $vd, $vm, $simm */
4450 { /* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr${p}.s64 $vd, $vm, $simm */
4453 { /* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr${p}.s16 $vd, $vm, $simm */
4456 { /* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr${p}.s32 $vd, $vm, $simm */
4459 { /* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr${p}.s16 $vd, $vm, $simm */
4462 { /* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr${p}.s8 $vd, $vm, $simm */
4465 { /* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr${p}.u8 $vd, $vm, $simm */
4468 { /* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr${p}.u64 $vd, $vm, $simm */
[all …]
DARMMapping.c700 { ARM_INS_VSHR, "vshr" },
/external/capstone/bindings/python/capstone/
Darm_const.py685 ARM_INS_VSHR = 383 variable
/external/capstone/bindings/java/capstone/
DArm_const.java688 public static final int ARM_INS_VSHR = 383; field in Arm_const
/external/capstone/include/capstone/
Darm.h828 ARM_INS_VSHR, enumerator
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc4441 { /* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr${p}.s8 $vd, $vm, $simm */
4444 { /* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr${p}.s64 $vd, $vm, $simm */
4447 { /* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr${p}.s32 $vd, $vm, $simm */
4450 { /* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr${p}.s64 $vd, $vm, $simm */
4453 { /* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr${p}.s16 $vd, $vm, $simm */
4456 { /* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr${p}.s32 $vd, $vm, $simm */
4459 { /* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr${p}.s16 $vd, $vm, $simm */
4462 { /* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr${p}.s8 $vd, $vm, $simm */
4465 { /* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr${p}.u8 $vd, $vm, $simm */
4468 { /* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr${p}.u64 $vd, $vm, $simm */
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