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Searched refs:CRMU_CFG_BASE (Results 1 – 3 of 3) sorted by relevance

/external/arm-trusted-firmware/plat/brcm/board/stingray/include/
Dscp_utils.h20 #define SCP_READ_CFG(cfg) mmio_read_32(CRMU_CFG_BASE + \
22 #define SCP_WRITE_CFG(cfg, value) mmio_write_32(CRMU_CFG_BASE + \
25 #define SCP_READ_CFG16(cfg) mmio_read_16(CRMU_CFG_BASE + \
27 #define SCP_WRITE_CFG16(cfg, value) mmio_write_16(CRMU_CFG_BASE + \
30 #define SCP_READ_CFG8(cfg) mmio_read_8(CRMU_CFG_BASE + \
32 #define SCP_WRITE_CFG8(cfg, value) mmio_write_8(CRMU_CFG_BASE + \
Dcrmu_def.h24 #define CRMU_CFG_BASE (CRMU_SHARED_SRAM_BASE + \ macro
/external/arm-trusted-firmware/plat/brcm/board/stingray/src/
Dbrcm_pm_ops.c404 mmio_write_64(CRMU_CFG_BASE + offsetof(M0CFG, core_cfg.rvbar), in plat_setup_psci_ops()