Searched refs:NumRegDefsLeft (Results 1 – 10 of 10) sorted by relevance
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 499 if (Pred.isCtrl() || (Pred.getSUnit()->NumRegDefsLeft == 0)) in scheduledNode()
501 --Pred.getSUnit()->NumRegDefsLeft; in scheduledNode()
527 ParallelLiveRanges += SU->NumRegDefsLeft; in scheduledNode()
558 SU->NumRegDefsLeft = NodeNumDefs; in initNumRegDefsLeft()
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| D | ScheduleDAGSDNodes.cpp | 511 if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) { in AddSchedEdges()
520 --OpSU->NumRegDefsLeft; in AddSchedEdges()
601 assert(SU->NumRegDefsLeft == 0 && "expect a new node"); in InitNumRegDefsLeft()
603 assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected"); in InitNumRegDefsLeft()
604 ++SU->NumRegDefsLeft; in InitNumRegDefsLeft()
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| D | ScheduleDAGRRList.cpp | 1100 !D.isCtrl() && NewSU->NumRegDefsLeft > 0) in TryUnfoldSU()
1101 --NewSU->NumRegDefsLeft; in TryUnfoldSU()
2093 if (PredSU->NumRegDefsLeft == 0) { in HighRegPressure()
2142 if (PredSU->NumRegDefsLeft == 0) { in RegPressureDiff()
2185 if (PredSU->NumRegDefsLeft == 0) { in scheduledNode()
2203 --PredSU->NumRegDefsLeft; in scheduledNode()
2204 unsigned SkipRegDefs = PredSU->NumRegDefsLeft; in scheduledNode()
2220 int SkipRegDefs = (int)SU->NumRegDefsLeft; in scheduledNode()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 274 unsigned short NumRegDefsLeft; // # of reg defs with no scheduled use.
312 NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
328 NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
343 NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 511 if (I->isCtrl() || (I->getSUnit()->NumRegDefsLeft == 0)) in scheduledNode()
513 --I->getSUnit()->NumRegDefsLeft; in scheduledNode()
540 ParallelLiveRanges += SU->NumRegDefsLeft; in scheduledNode()
570 SU->NumRegDefsLeft = NodeNumDefs; in initNumRegDefsLeft()
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| D | ScheduleDAGSDNodes.cpp | 494 if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) { in AddSchedEdges()
503 --OpSU->NumRegDefsLeft; in AddSchedEdges()
584 assert(SU->NumRegDefsLeft == 0 && "expect a new node"); in InitNumRegDefsLeft()
586 assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected"); in InitNumRegDefsLeft()
587 ++SU->NumRegDefsLeft; in InitNumRegDefsLeft()
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| D | ScheduleDAGRRList.cpp | 1068 && !D.isCtrl() && NewSU->NumRegDefsLeft > 0) in CopyAndMoveSuccessors()
1069 --NewSU->NumRegDefsLeft; in CopyAndMoveSuccessors()
1952 if (PredSU->NumRegDefsLeft == 0) { in HighRegPressure()
2001 if (PredSU->NumRegDefsLeft == 0) { in RegPressureDiff()
2044 if (PredSU->NumRegDefsLeft == 0) { in scheduledNode()
2062 --PredSU->NumRegDefsLeft; in scheduledNode()
2063 unsigned SkipRegDefs = PredSU->NumRegDefsLeft; in scheduledNode()
2079 int SkipRegDefs = (int)SU->NumRegDefsLeft; in scheduledNode()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 272 unsigned short NumRegDefsLeft = 0; ///< # of reg defs with no scheduled use. variable
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAG.cpp | 330 dbgs() << " # rdefs left : " << NumRegDefsLeft << "\n"; in dumpAll()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ScheduleDAG.cpp | 348 dbgs() << " # rdefs left : " << NumRegDefsLeft << "\n"; in dumpAttributes()
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