Home
last modified time | relevance | path

Searched refs:SXTH (Results 1 – 25 of 55) sorted by relevance

123

/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h46 SXTH, enumerator
65 case AArch64_AM::SXTH: return "sxth"; in getShiftExtendName()
132 case 5: return AArch64_AM::SXTH; in getExtendType()
159 case AArch64_AM::SXTH: return 5; break; in getExtendEncoding()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h46 SXTH, enumerator
65 case AArch64_AM::SXTH: return "sxth"; in getShiftExtendName()
132 case 5: return AArch64_AM::SXTH; in getExtendType()
159 case AArch64_AM::SXTH: return 5; break; in getExtendEncoding()
/external/vixl/test/aarch32/config/
Dcond-rd-operand-rn-t32.json57 "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> ; T1
58 // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
Dcond-rd-operand-rn-ror-amount-a32.json34 "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
Dcond-rd-operand-rn-ror-amount-t32.json34 "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
Dcond-rd-operand-rn-a32.json48 "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
/external/llvm/test/CodeGen/AArch64/
Dbitfield-extract.ll84 ; SHR with multiple uses is fine as SXTH and SBFX are both aliases of SBFM.
/external/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt503 # SXTB/SXTH
Dthumb2.txt2193 # SXTH
2247 # SXTH
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h365 SXTH, enumerator
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc82 COMPARE_MACRO(Mov(w14, Operand(w15, SXTH, 2)), "sbfiz w14, w15, #2, #16"); in TEST()
343 COMPARE(adds(w21, w22, Operand(w23, SXTH, 2)), "adds w21, w22, w23, sxth #2"); in TEST()
347 COMPARE(cmn(x2, Operand(x3, SXTH, 4)), "cmn x2, w3, sxth #4"); in TEST()
369 COMPARE(subs(w21, w22, Operand(w23, SXTH, 2)), "subs w21, w22, w23, sxth #2"); in TEST()
2407 COMPARE_MACRO(Csel(x3, x4, Operand(x5, SXTH), eq), in TEST()
2412 Operand(x5, SXTH), in TEST()
2427 COMPARE_MACRO(Csel(x9, Operand(x10, SXTH), x11, eq), in TEST()
2431 Operand(x10, SXTH), in TEST()
Dtest-assembler-aarch64.cc191 __ Mvn(x13, Operand(x2, SXTH, 3)); in TEST()
365 __ Mov(x26, Operand(x13, SXTH, 3)); in TEST()
419 __ Mov(w22, Operand(w11, SXTH, 1)); in TEST()
426 __ Mov(x28, Operand(x12, SXTH, 1)); in TEST()
502 __ Orr(x11, x0, Operand(x1, SXTH, 1)); in TEST()
596 __ Orn(x11, x0, Operand(x1, SXTH, 1)); in TEST()
663 __ And(x11, x0, Operand(x1, SXTH, 1)); in TEST()
809 __ Bic(x11, x0, Operand(x1, SXTH, 1)); in TEST()
941 __ Eor(x11, x0, Operand(x1, SXTH, 1)); in TEST()
1008 __ Eon(x11, x0, Operand(x1, SXTH, 1)); in TEST()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h463 SXTH, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedPredicates.td23 def CheckExtSXTH : CheckImmOperand_s<3, "AArch64_AM::SXTH">;
/external/llvm/test/MC/ARM/
Dbasic-thumb-instructions.s638 @ SXTB/SXTH
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp302 STORE_OPCODE(SEXT16, SXTH); in OpcodeCache()
DARMFastISel.cpp2662 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2902 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
DARMScheduleR52.td215 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
DARMScheduleSwift.td161 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp2643 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2883 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
DARMScheduleSwift.td157 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
/external/pcre/src/sljit/
DsljitNativeARM_T2_32.c185 #define SXTH 0xb200 macro
830 return push_inst16(compiler, SXTH | RD3(dst) | RN3(arg2)); in emit_op_imm()
DsljitNativeARM_32.c145 #define SXTH 0xe6bf0070 macro
1473 return push_inst(compiler, (op == SLJIT_MOV_U16 ? UXTH : SXTH) | RD(dst) | RM(src2)); in emit_single_op()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1252 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend()
1265 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend64()
2755 .Case("sxth", AArch64_AM::SXTH) in tryParseOptionalShiftExtend()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp989 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend()
2394 .Case("sxth", AArch64_AM::SXTH) in tryParseOptionalShiftExtend()

123