Searched refs:Src1Regs (Results 1 – 3 of 3) sorted by relevance
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
D | LegalizerHelper.cpp | 727 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; in narrowScalar() local 728 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs); in narrowScalar() 737 MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]); in narrowScalar() 739 MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i], in narrowScalar() 762 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; in narrowScalar() local 763 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs); in narrowScalar() 769 {Src1Regs[0], Src2Regs[0]}); in narrowScalar() 777 {Src1Regs[i], Src2Regs[i], BorrowIn}); in narrowScalar() 2412 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; in fewerElementsVectorBasic() local 2417 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs); in fewerElementsVectorBasic() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | AMDGPURegisterBankInfo.cpp | 1590 SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2)); in applyMappingImpl() local 1595 assert(Src1Regs.empty() && Src2Regs.empty()); in applyMappingImpl() 1599 if (Src1Regs.empty()) in applyMappingImpl() 1600 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg()); in applyMappingImpl() 1602 setRegsToType(MRI, Src1Regs, HalfTy); in applyMappingImpl() 1612 B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]); in applyMappingImpl() 1613 B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]); in applyMappingImpl() 1670 SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2)); in applyMappingImpl() local 1674 assert(Src0Regs.empty() && Src1Regs.empty()); in applyMappingImpl() 1679 assert(Src0Regs.size() == Src1Regs.size() && in applyMappingImpl() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
D | LegalizerHelper.h | 170 ArrayRef<Register> Src1Regs,
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